The silicon direct bonding (SDB) is an important technology, and has been widely applied to SOI, MEMS and high power devices. For the high power device, the impurity profile, interfacial oxide and voids have large effect on the breakdown voltage and the serial resistance owing to the large current and high reverse-bias voltage at the bonding interface. So the silicon bonding technology applied to high power devices is required to have a good quality, one of the most difficult bonding technology, but it is very important and worth studying.

In the paper, the studies are focus on the silicon direct bonding technology applied to the high power devices, including the studies on the bonding process mechanism to eliminate the voids at the bonding interface, the studies on the bonding process model to simulate the impurity distribution and the studies on the fabrication of the large power and high breakdown voltage p-i-n diode by the silicon direct bonding technology.

First, the mechanism of bonding process is studied and the “open-close” effect is presented during the annealing process. the “open-close” effect is proposed based on lots of experiments and theoretical analysis and the bonding interface is considered to have a “open-close” in very short time if the annealing temperature is over 900℃. The “open-close” effect has large effect on the formation of the voids at the bonding interface. If the “open-close” is insufficient, the voids will form and not easy to eliminate.

Second, the bonding process models are studied, mainly including the three respects: (1) The impurity distribution model: It is effected by the annealing temperature, the annealing time, the type and concentration of the impurity, the interfacial oxide layer and so on. the “pile-up” and “extraction” effect: It is present at the interface if the diffusion coefficients are different in dissimilar materials. (2) The stress distribution at the bonding interface: Including the elasticity stresses of the bonding at room temperature, the thermal stresses and viscidity stresses during the high temperature annealing, and the stresses brought by the voids and particulates at the bonding interface. (3) The bonding strength: It is mainly effected by the annealing temperature and the annealing time. Among the studies, the impurity distribution is emphased. Based on the studies on the bonding process and bonding models, the simulation software is developed by Matlab tool, which provides an important tool in process design.

Finally, the hydrophobic bonding technology is studied which is applied to the fabrication of the p-i-n diode. Compared with the epitaxy technology, the bonding technology have evident advantage: the step impurity profile, the small defect concentration in N^- or P^- layer, the long minority carrier lifetime, the small serial resistance. The electrical properties of the p-i-n fabricated by the bonding wafers are evidently better than by the epitaxial wafers, which have been proved by the experiments on the flow processing line. In addition, to avoid the effect of the defects at the bonding interface on the electrical properties, a new structure has been presented to improve the bonding technology, which integrates both advantages of the bonding technology and the epitaxy technology.

By the in-depth investigation in theory and experiments, a set of the mature process flows of the silicon direct bonding have come into use, and the free-void binding wafers have been made. The results of the measured results in practice and the simulated results are identical. The high-voltage p-i-n diodes have been fabricated by our bonding wafers in No.970 factory, showing that electrical properties are evidently better than those of the former epitaxy wafers.