AD9515 Datasheet

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AD9515

Table 13. S5, S6, and S7鈥擮UT1

S5

0

1/3

2/3

1

0

1/3

2/3

1

0

1/3

2/3

1

0

1/3

2/3

1

0

1/3

2/3

1

0

1/3

2/3

1

0

1/3

2/3

1

0

1/3

2/3

1

0

1/3

2/3

1

0

1/3

2/3

1

0

1/3

2/3

1

0

1/3

2/3

1

0

S6

0

0

0

0

1/3

1/3

1/3

1/3

2/3

2/3

2/3

2/3

1

1

1

1

0

0

0

0

1/3

1/3

1/3

1/3

2/3

2/3

2/3

2/3

1

1

1

1

0

0

0

0

1/3

1/3

1/3

1/3

2/3

2/3

2/3

2/3

1

1

1

1

0

S7

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1/3

1/3

1/3

1/3

1/3

1/3

1/3

1/3

1/3

1/3

1/3

1/3

1/3

1/3

1/3

1/3

2/3

2/3

2/3

2/3

2/3

2/3

2/3

2/3

2/3

2/3

2/3

2/3

2/3

2/3

2/3

2/3

1

OUT1

Divide (Duty Cycle

1

)

1

2 (50%)

3 (33%)

4 (50%)

5 (40%)

6 (50%)

7 (43%)

8 (50%)

9 (44%)

10 (50%)

11 (45%)

12 (50%)

OUT1 OFF

14 (50%)

15 (47%)

16 (50%)

17 (47%)

18 (50%)

19 (47%)

20 (50%)

21 (48%)

22 (50%)

23 (48%)

24 (50%)

25 (48%)

26 (50%)

27 (48%)

28 (50%)

29 (48%)

30 (50%)

31 (48%)

32 (50%)

2 (50%)

4 (50%)

4 (50%)

4 (50%)

8 (50%)

8 (50%)

8 (50%)

8 (50%)

8 (50%)

8 (50%)

8 (50%)

16 (50%)

16 (50%)

16 (50%)

16 (50%)

16 (50%)

16 (50%)

OUT1

Phase

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

2

3

1

2

3

4

5

6

7

1

2

3

4

5

6

S5

1/3

2/3

1

0

1/3

2/3

1

0

1/3

2/3

1

0

1/3

2/3

1

1

S6

0

0

0

1/3

1/3

1/3

1/3

2/3

2/3

2/3

2/3

1

1

1

1

S7

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

OUT1

Divide (Duty Cycle

1

)

16 (50%)

16 (50%)

16 (50%)

16 (50%)

16 (50%)

16 (50%)

16 (50%)

16 (50%)

16 (50%)

32 (50%)

32 (50%)

32 (50%)

32 (50%)

32 (50%)

Do not use

OUT1

Phase

7

8

9

10

11

12

13

14

15

1

2

3

4

5

Duty cycle is the clock signal high time divided by the total period.

Table 14. S8鈥擮UT0/OUT1 Phase (Delay) Select

(Used with S9 to S10)

S8

0

1/3

2/3

1

OUT0

No Phase

Phase

No Phase

Phase (Start High)

OUT1 (Delay if S0 鈮?0)

Phase (Delay)

No Phase

Phase (Delay) (Start High)

No Phase

Table 15. S9 and S10

OUT0 or OUT1 Phase

(Depends on S8)

Phase

1

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

OUT1 Delay (S0 鈮?0)

(Depends on S8)

Fine Delay

0

1/16

1/8

3/16

1/4

5/16

3/8

7/16

1/2

9/16

5/8

11/16

3/4

13/16

7/8

15/16

S9

0

1/3

2/3

1

0

1/3

2/3

1

0

1/3

2/3

1

0

1/3

2/3

1

1

S10

0

0

0

0

1/3

1/3

1/3

1/3

2/3

2/3

2/3

2/3

1

1

1

1

A phase > 0 in Table 12 or overrides the phase in Table 15.

Rev. 0 | Page 21 of 28

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