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AD9515 Datasheet

  • AD9515

  • 1.6 GHz Clock Distribution IC, Dividers,Delay Adjust, Two Ou...

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  • 29页

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AD9515
SPECIFICATIONS
Typical (typ) is given for V
S
= 3.3 V 卤 5%, T
A
= 25掳C, R
SET
= 4.12 k惟, LVPECL swing = 790 mV, unless otherwise noted. Minimum (min)
and maximum (max) values are given over full V
S
and T
A
(鈭?0掳C to +85掳C) variation.
CLOCK INPUT
Table 1.
Parameter
CLOCK INPUT (CLK)
Input Frequency
1
Input Sensitivity
1
Input Common-Mode Voltage, V
CM
Input Common-Mode Range, V
CMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
1
Min
0
1.5
1.3
4.0
Typ
Max
1.6
Unit
GHz
mV p-p
V
V
mV p-p
k惟
pF
Test Conditions/Comments
150
1.6
150
4.8
2
1.7
1.8
5.6
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLKB ac-bypassed to RF ground
Self-biased
A slew rate of 1 V/ns is required to meet jitter, phase noise, and propagation delay specifications.
CLOCK OUTPUTS
Table 2.
Parameter
LVPECL CLOCK OUTPUT
(OUT0) Differential
Output Frequency
Output High Voltage (V
OH
)
Output Low Voltage (V
OL
)
Output Differential Voltage (V
OD
)
LVDS CLOCK OUTPUT
(OUT1) Differential
Output Frequency
Differential Output Voltage (V
OD
)
Delta V
OD
Output Offset Voltage (V
OS
)
Delta V
OS
Short-Circuit Current (I
SA
, I
SB
)
CMOS CLOCK OUTPUT
(OUT1) Single-Ended
Output Frequency
Output Voltage High (V
OH
)
Output Voltage Low (V
OL
)
Min
Typ
Max
Unit
Test Conditions/Comments
Termination = 50 惟 to V
S
鈭?2 V
0
V
S
鈭?1.1
V
S
鈭?1.90
640
V
S
鈭?0.96
V
S
鈭?1.76
790
1.6
V
S
鈭?0.82
V
S
鈭?1.52
960
GHz
V
V
mV
Termination = 100 惟 differential
0
250
1.125
350
1.23
14
800
450
30
1.375
25
24
MHz
mV
mV
V
mV
mA
0
V
S
鈭?0.1
250
0.1
MHz
V
V
Output shorted to GND
Single-ended measurements; termination open
Complementary output on (OUT1B)
With 5 pF load
@ 1 mA load
@ 1 mA load
Rev. 0 | Page 3 of 28

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