AD9515 Datasheet

IC型号：
AD9515
PDF描述：
1.6 GHz Clock Distribution IC, Dividers,Delay Adjust, Two Ou...
文件大小：
1882.42KB
PDF页数：
29页
芯片厂家：
AD

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AD9515

Parameter

CLK = 491.52 MHz, OUT = 122.88 MHz

Divide = 4

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

>10 MHz Offset

CLK = 245.76 MHz, OUT = 245.76 MHz

Divide = 1

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

>10 MHz Offset

CLK = 245.76 MHz, OUT = 122.88 MHz

Divide = 2

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

>10 MHz Offset

CLK-TO-CMOS ADDITIVE PHASE NOISE

CLK = 245.76 MHz, OUT = 245.76 MHz

Divide = 1

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

>10 MHz Offset

CLK = 245.76 MHz, OUT = 61.44 MHz

Divide = 4

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

>10 MHz Offset

Min

Typ

Max

Unit

Test Conditions/Comments

鈭?18

鈭?29

鈭?36

鈭?47

鈭?53

鈭?56

鈭?58

dBc/Hz

鈭?08

鈭?18

鈭?28

鈭?38

鈭?45

鈭?48

鈭?55

dBc/Hz

鈭?18

鈭?27

鈭?37

鈭?47

鈭?54

鈭?56

鈭?58

dBc/Hz

鈭?10

鈭?21

鈭?30

鈭?40

鈭?45

鈭?49

鈭?56

dBc/Hz

鈭?25

鈭?32

鈭?43

鈭?52

鈭?58

鈭?60

鈭?62

dBc/Hz

Rev. 0 | Page 7 of 28

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