24LC65
5.7
Security Options
6.0
ACKNOWLEDGE POLLING
The 24LC65 has a sophisticated mechanism for
write-protecting portions of the array. This write protect
function is programmable and allows the user to protect
0-15 contiguous 4K blocks. The user sets the security
option by sending to the device the starting block num-
ber for the protected region and the number of blocks to
be protected. If the security option is invoked with 0
blocks protected, then all portions of the array will be
unprotected. All parts will come from the factory in the
default con铿乬uration with the starting block number set
to 15 and the number of protected blocks set to zero.
THE SECURITY OPTION CAN BE SET ONLY ONCE.
To invoke the security option, a write command is sent
to the device with the leading bit (bit 7) of the 铿乺st
address byte set to a 1 (Figure 8-1). Bits 1-4 of the 铿乺st
address byte de铿乶e the starting block number for the
protected region. For example, if the starting block
number is to be set to 5, the 铿乺st address byte would be
1XX0101X. Bits 0, 5 and 6 of the 铿乺st address byte are
disregarded by the device and can be either high or low.
The device will acknowledge after the 铿乺st address
byte. A byte of don鈥檛 care bits is then sent by the master,
with the device acknowledging afterwards. The third
byte sent to the device has bit 7 (S/HE) set high and bit
6 (R) set low. Bits 4 and 5 are don鈥檛 cares and bits 0-3
de铿乶e the number of blocks to be write protected. For
example, if three blocks are to be protected, the third
byte would be 10XX0011. After the third byte is sent to
the device, it will acknowledge and a STOP bit is then
sent by the master to complete the command.
During a normal write sequence, if an attempt is made
to write to a protected address, no data will be written
and the device will not report an error or abort the com-
mand. If a write command is attempted across a
secure boundary, unprotected addresses will be written
and protected addresses will not.
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 6-1 for 铿俹w diagram.
FIGURE 6-1:
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
5.8
Security Con铿乬uration Read
Did Device
Acknowledge
(ACK = 0)?
YES
Next
Operation
NO
The status of the secure portion of memory can be read
by using the same technique as programming this
option except the READ bit (bit 6) of the con铿乬uration
byte is set to a one. After the con铿乬uration byte is sent,
the device will acknowledge and then send two bytes of
data to the master just as in a normal read sequence.
The master must acknowledge the 铿乺st byte and not
acknowledge the second, and then send a stop bit to
end the sequence. The upper four bits of both of these
bytes will always be read as '1's. The lower four bits of
the 铿乺st byte contains the starting secure block. The
lower four bits of the second byte contains the number
of secure blocks. The default starting secure block is 铿乫-
teen and the default number of secure blocks is zero
(Figure 8-1).
DS21073E-page 8
漏
1996 Microchip Technology Inc.
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