DS1621 Datasheet

  • DS1621

  • Digital Thermometer and Thermostat

  • 647.51KB

  • Dallas

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DS1621
NOTES:
1. All voltages are referenced to ground.
2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
DD
is switched off.
3. I
CC
specified with T
OUT
pin open.
4. I
CC
specified with V
CC
at 5.0V and SDA, SCL = 5.0V, 0掳C to 70掳C.
5. After this period, the first clock pulse is generated.
6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
V
IH MIN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7. The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the
SCL signal.
8. A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
>250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t
RMAX
+t
SU:DAT
= 1000+250 = 1250 ns before the SCL line is released.
9. C
b
鈥?total capacitance of one bus line in pF.
10. Writing to the nonvolatile memory should only take place in the 0掳 to 70掳 temperature range.
C
C
11. See typical curve for specification limits outside 0掳C to 70掳C range. Thermometer error reflects
sensor accuracy as tested during calibration.
TIMING DIAGRAM
15 of 16
102299

DS1621 产品属性

  • Lead (SnPb) Finish for COTSObsolescence Mitigation Program

  • 50

  • 集成电路 (IC)

  • PMIC - 热管理

  • -

  • 温度计,恒温计

  • 内部

  • -55°C ~ 125°C

  • ±2°C(最小值)

  • ADC(三角积分型),比较器,寄存器库

  • I²C?/SMBus?

  • 2.7 V ~ 5.5 V

  • -55°C ~ 125°C

  • 通孔

  • 8-DIP(0.300",7.62mm)

  • 8-DIP

  • 管件

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