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24LC41数据手册封面

24LC41 Datasheet

  • 24LC41

  • 1K/4K 2.5V Dual Mode, Dual Port I 2 C ? Serial EEPROM

  • 140.45KB

  • Microchip

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24LC41
TABLE 1-3:
AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS
PORTS)
DDC Monitor Port (Bi-directional Mode) and Microcontroller Access Port
Standard Mode
Parameter
Clock frequency (DSCL and
MSCL)
Clock high time (DSCL and
MSCL)
Clock low time (DSCL and
MSCL)
DSCL, DSDA, MSCL &
MSDA rise time
DSCL, DSDA, MSCL &
MSDA fall time
START condition hold time
Symbol
Min
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
鈥?/div>
4000
4700
鈥?/div>
鈥?/div>
4000
4700
0
250
4000
鈥?/div>
4700
Max
100
鈥?/div>
鈥?/div>
1000
300
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
3500
鈥?/div>
Vcc = 4.5 - 5.5V
Fast Mode
Min
鈥?/div>
600
1300
鈥?/div>
鈥?/div>
600
600
0
100
600
鈥?/div>
1300
Max
400
鈥?/div>
鈥?/div>
300
300
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
900
鈥?/div>
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
After this period the 铿乺st
clock pulse is generated
Only relevant for repeated
START condition
(Note 2)
Units
Remarks
START condition setup time T
SU
:
STA
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
Output fall time from V
IH
min to V
IL
max
Input 铿乴ter spike suppres-
sion (DSCL, DSDA, MSCL
& MSDA pins)
Write cycle time
T
OF
T
SP
鈥?/div>
鈥?/div>
250
50
20 + .1
C
B
鈥?/div>
250
50
ns
ns
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1), C
B
鈮?/div>
100 pF
(Note 3)
T
WR
鈥?/div>
10
鈥?/div>
鈥?/div>
600
1300
鈥?/div>
0
10M
10
1000
鈥?/div>
鈥?/div>
500
鈥?/div>
鈥?/div>
ms
ns
ns
ns
ns
ns
cycles
Byte or Page mode
DDC Monitor Port Transmit-Only Mode Parameters
Output valid from VCLK/
T
VAA
鈥?/div>
2000
DWP
T
VHIGH
VCLK/DWP high time
4000
鈥?/div>
4700
鈥?/div>
VCLK/DWP low time
T
VLOW
Mode transition time
T
VHZ
鈥?/div>
500
Transmit-Only power up
T
VPU
0
鈥?/div>
time
Endurance
鈥?/div>
10M
鈥?/div>
25
掳
C, Vcc = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the unde铿乶ed region
(minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of START or STOP
conditions.
3: The combined T
SP
and V
HYS
speci铿乧ations are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
I
speci铿乧ation for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a speci铿乧
application, please consult the Total Endurance Model which can be obtained on our BBS or website.
漏
1996 Microchip Technology Inc.
DS21140B-page 3

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