24LC41
FIGURE 3-1:
DSCL
or
MSCL
(
A
)
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D)
(D)
(C)
(
A
)
DSDA
or
MSDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
FIGURE 3-2:
BUS TIMING START/STOP
V
HYS
MSCL
or
MSCL
IN
DSDA
or
MSDA
IN
T
SU
:
STA
T
HD
:
STA
T
SU
:
STO
START
STOP
FIGURE 3-3:
BUS TIMING DATA
T
F
T
HIGH
T
LOW
T
R
DSCL
or
MSCL
T
SU
:
STA
IN
DSDA
OR
T
HD
:
DAT
T
HD
:
STA
T
SP
T
AA
T
HD
:
STA
T
SU
:
DAT
T
SU
:
STO
MSDA
IN
T
AA
T
BUF
DSDA
OR
MSDA
OUT
FIGURE 3-4:
START
CONTROL BYTE ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W
A
1
0
1
0
X
X
X
X = Don鈥檛 care. B0 is don鈥檛 care for DDC Monitor Port, but is
used by the Microcontroller Access Port to select which of
the two 256 word blocks of memory are to be accessed.
漏
1996 Microchip Technology Inc.
DS21140B-page 7