ADS5424 Datasheet_PDF文件下载_芯片资料查询

ADS5424

www.ti.com

SLWS157A 鈭?JANUARY 2005 鈭?REVISED MAY 2005

APPLICATION INFORMATION

THEORY OF OPERATION

The ADS5424 is a 14 bit, 105 MSPS, monolithic

pipeline analog to digital converter. Its bipolar analog

core operates from a 5 V supply, while the output uses

3.3 V supply for compatibility with the CMOS family. The

conversion process is initiated by the rising edge of the

external input clock. At that instant, the differential input

signal is captured by the input track and hold (T&H) and

the input sample is sequentially converted by a series

of small resolution stages, with the outputs combined in

a digital correction logic block. Both the rising and the

falling clock edges are used to propagate the sample

through the pipeline every half clock cycle. This process

results in a data latency of three clock cycles, after

which the output data is available as a 14 bit parallel

word, coded in binary two鈥檚 complement format.

of 2.2 V

PP

. The maximum swing is determined by the

internal reference voltage generator eliminating any

external circuitry for this purpose.

The ADS5424 obtains optimum performance when the

analog inputs are driven differentially. The circuit in

Figure 38 shows one possible configuration using an

RF transformer with termination either on the primary or

on the secondary of the transformer. If voltage gain is

required a step up transformer can be used. For higher

gains that would require impractical higher turn ratios on

the transformer, a single-ended amplifier driving the

transformer can be used (see Figure 39). Another

circuit optimized for performance would be the one on

Figure 40, using the THS4304 or the OPA695. Texas

Instruments has shown excellent performance on this

configuration up to 10 dB gain with the THS4304 and at

14 dB gain with the OPA695. For the best performance,

they need to be configured differentially after the

transformer (as shown) or in inverting mode for the

OPA695 (see SBAA113); otherwise, HD2 from the op

amps limits the useful frequency.

INPUT CONFIGURATION

The analog input for the ADS5424 (see Figure 32)

consists of an analog differential buffer followed by a

bipolar track-and-hold. The analog buffer isolates the

source driving the input of the ADC from any internal

switching. The input common mode is set internally

through a 500

鈩?/div>

resistor connected from 2.4 V to each

of the inputs. This results in a differential input

impedance of 1 k鈩?

For a full-scale differential input, each of the differential

lines of the input signal (pins 11 and 12) swings

symmetrically between 2.4 +0.55 V and 2.4 鈥?.55 V.

This means that each input is driven with a signal of up

to 2.4

卤0.55

V, so that each input has a maximum signal

swing of 1.1 V

PP

for a total differential input signal swing

5V

VIN

+

OPA695

鈭?/div>

R1

400

鈩?/div>

R2

57.5

鈩?/div>

AV = 8V/V

(18 dB)

鈭? V

RS

100

鈩?/div>

0.1

碌F

R

0

50W

Z

0

50W

1:1

AIN

R

50W

ADS5424

AIN

ADT1鈭?/div>

1WT

AC Signal

Source

Figure 38. Converting a Single-Ended Input to a

Differential Signal Using RF Transformers

1:1

RT

100

鈩?/div>

RIN

CIN

AIN

ADS5424

AIN

1000

碌F

Figure 39. Using the OPA695 With the ADS5424

17

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