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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC9774/D

Rev 1, 04/2002

Product Preview

3.3V/2.5V 1:14 LVCMOS PLL

Clock Generator

The MPC9774 is a 3.3V or 2.5V compatible, 1:14 PLL based clock

generator targeted for high performance low-skew clock distribution in

mid-range to high-performance networking, computing and telecom

applications. With output frequencies up to 125 MHz and output skews

less than 300 ps1 the device meets the needs of the most demanding

clock applications.

Features

鈥?/div>

1:14 PLL based low-voltage clock generator

MPC9774

3.3V/2.5V 1:14 LVCMOS

PLL CLOCK GENERATOR

鈥?/div>

2.5V or 3.3V power supply

Internal power鈥搊n reset

Generates clock signals up to 125 MHz

Maximum output skew of 300 ps1

Two LVCMOS PLL reference clock inputs

External PLL feedback supports zero-delay capability

Various feedback and output dividers (see application section)

Supports up to three individual generated output clock frequencies

Drives up to 28 clock lines

Ambient temperature range 0掳C to +85掳C

Pin and function compatible to the MPC974

FA SUFFIX

52 LEAD LQFP PACKAGE

CASE 848D

Functional Description

The MPC9774 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

MPC9774 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The

reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match

the VCO frequency range.

The MPC9774 features frequency programmability between the three output banks outputs as well as the output to input

relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2 and 3:2:1 can be realized. Additionally, the device supports a separate

configurable feedback output which allows for a wide variety of of input/output frequency multiplication alternatives. The

VCO_SEL pin provides an extended PLL input reference frequency range.

The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two

alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL

bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output

dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL

characteristics do not apply.

The MPC9774 has an internal power鈥搊n reset.

The MPC9774 is fully 2.5V and 3.3V compatible and requires no external loop filter components. All inputs (except XTAL)

accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50

鈩?/div>

transmission lines. For series terminated transmission lines, each of the MPC9774 outputs can drive one or two traces giving the

devices an effective fanout of 1:12. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP

package.

1. Final specification of this parameter is pending characterization.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

漏

Motorola, Inc. 2002

1

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