鈥?/div>
Clock Distribution for Pentium鈩?Systems with PCI
2 Selectable LVCMOS/LVTTL Clock Inputs
350ps Output to Output Skew
Drives up to 20 Independent Clock Lines
Maximum Input/Output Frequency of 150MHz
Tristatable Outputs
32鈥揕ead TQFP Packaging
3.3V VCC Supply
With an output impedance of approximately 7鈩? in both the HIGH and
the LOW logic states, the output buffers of the MPC946 are ideal for
FA SUFFIX
driving series terminated transmission lines. More specifically each of the
TQFP PACKAGE
10 MPC946 outputs can drive two series terminated transmission lines.
CASE 873A鈥?2
With this capability, the MPC946 has an effective fanout of 1:20 in
applications using point鈥搕o鈥損oint distribution schemes.
The MPC946 has the capability of generating 1X and 1/2X signals from
a 1X source. The design is fully static, the signals are generated and
retimed inside the chip to ensure minimal skew between the 1X and 1/2X
signals. The device features selectability to allow the user to select the
ratio of 1X outputs to 1/2X outputs.
Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to
provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the
TCLK1 input is selected.
All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the
Dsel pins will select the 1X output. The MR/Tristate input will reset the internal flip flops and tristate the outputs when it is forced
HIGH.
The MPC946 is fully 3.3V compatible. The 32鈥搇ead TQFP package was chosen to optimize performance, board space and
cost of the device. The 32鈥搇ead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.
Pentium is a trademark of Intel Corporation.
10/96
漏
Motorola, Inc. 1996
1
REV 1
1
2
3
4
5
6
