MPC958 Datasheet

IC型号：
MPC958
PDF描述：
Low Voltage PLL Clock Drlver
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104.74KB
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MOTOROLA

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MPC958/D

Low Voltage PLL Clock Driver

The MPC958 is a 3.3V compatible, PLL based clock driver device

targeted for high performance clock tree designs. With output frequencies

of up to 200MHz and output skews of 200ps the MPC958 is ideal for the

most demanding clock tree designs. The devices employ a fully

differential PLL design to minimize cycle鈥搕o鈥揷ycle and phase jitter.

MPC958

鈥?/div>

Fully Integrated PLL

鈥?/div>

Output Frequency up to 200MHz

LOW VOLTAGE

PLL CLOCK DRIVER

Freescale Semiconductor, Inc...

鈥?/div>

Outputs Disable in High Impedance

鈥?/div>

LQFP Packaging

鈥?/div>

100ps Cycle鈥搕o鈥揅ycle Jitter

The MPC958 has a differential LVPECL reference input along with an

external feedback input. These features make the MPC958 ideal for use

as a zero delay, low skew fanout buffer. The device performance has

been tuned and optimized for zero delay performance. The MR/OE input

pin will tristate the output buffers when driven 鈥渉igh鈥?

The MPC958 is fully 3.3V compatible and requires no external loop

filter components. All control inputs accept LVCMOS or LVTTL

compatible levels while the outputs provide LVCMOS levels with the

ability to drive terminated 50鈩?transmission lines. For series terminated

50鈩?lines, each of the MPC958 outputs can drive two traces giving the

device an effective fanout of 1:22. The device is packaged in a 7x7mm

32鈥搇ead LQFP package to provide the optimum combination of board

density and performance.

FA SUFFIX

32鈥揕EAD LQFP PACKAGE

CASE 873A鈥?2

QFB

(Int pull up)

PECL_CLK

(Int pull down)

PECL_CLK

FB_CLK

VCO_SEL

BYPASS

MR/OE

PLL_EN

(Int pull up)

Phase

Detector

LPF

VCO

200鈥?00MHz

梅2

Q0:8

(Int pull up)

(Int pull down)

(Int pull up)

Figure 1. Logic Diagram

06/00

漏

Motorola, Inc. 2000

For More Information On This Product,

REV 1

Go to: www.freescale.com

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