MPC9330 Datasheet

IC型号：
MPC9330
PDF描述：
3.3V 1:6 VLCMOS PLL Clock Generator
文件大小：
136.03KB
芯片厂家：
Motorola

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MPC9330

versus Dual Line Termination Waveforms鈥?shows a step in

the waveform, this step is caused by the impedance

mismatch seen looking into the driver. The parallel

combination of the 36鈩?series resistor plus the output

impedance does not match the parallel combination of the

line impedances. The voltage wave launched down the two

lines will equal:

VL = VS ( Z0

梅

(RS+R0 +Z0))

Z0 = 50鈩?|| 50鈩?/div>

RS = 36鈩?|| 36鈩?/div>

R0 = 14鈩?/div>

VL = 3.0 ( 25

梅

(18+17+25)

= 1.31V

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.6V. It will then increment

towards the quiescent 3.0V in steps separated by one round

trip delay (in this case 4.0ns).

1. Final skew data pending specification.

3.0

OutA

tD = 3.8956

OutB

tD = 3.9386

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines the

situation in Figure 6. 鈥淥ptimized Dual Line Termination鈥?/div>

should be used. In this case the series terminating resistors

are reduced such that when the parallel combination is added

to the output buffer impedance the line impedance is perfectly

matched.

MPC9330

OUTPUT

BUFFER

14鈩?/div>

RS = 22鈩?/div>

ZO = 50鈩?/div>

RS = 22鈩?/div>

ZO = 50鈩?/div>

14鈩?+ 22鈩?/div>

22鈩?= 50鈩?/div>

50鈩?/div>

25鈩?= 25鈩?/div>

Figure 6. Optimized Dual Line Termination

2.5

VOLTAGE (V)

2.0

1.5

1.0

0.5

TIME (nS)

Figure 5. Single versus Dual Waveforms

MPC9330 DUT

Pulse

Generator

Z = 50

ZO = 50鈩?/div>

RT = 50鈩?/div>

VTT

RT = 50鈩?/div>

VTT

Figure 7. CCLK MPC9330 AC test reference for Vcc = 3.3V and Vcc = 2.5V

MOTOROLA

TIMING SOLUTIONS

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