MPC9330 Datasheet

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MPC9330

VCC

25k

XTAL_IN

XTAL_OUT

CCLK

REF_SEL

25k

FB_IN

25k

VCC

FB_SEL

25k

VCC

25k

PWR_DN

VCC

25k

1

FB

0

梅16

Bank A

XTAL

0

1

Ref

VCO

梅2

梅4

0

1

1

0

梅2

梅4

梅6

Bank B

QB0

0

1

CLK

STOP

QB1

Bank C

QC0

0

1

CLK

STOP

QC1

0

1

CLK

STOP

QA1

QA0

PLL

PLL_EN

FSELA

FSELB

FSELC

3 x 25k

CLK_STOP0

CLK_STOP1

OE/MR

VCC

3 x 25k

3

Figure 1. MPC9330 Logic Diagram

REF_SEL

PLL_EN

18

FB_SEL

GND

VCC

QB0

QB1

24

GND

QA1

QA0

VCC

FSELA

FSELB

FSELC

NC

25

26

27

28

23

22

21

20

19

NC

17

16

15

14

13

GND

QC1

QC0

VCC

FB_IN

CLK_STOP1

CLK_STOP0

NC

12

11

10

9

8

GND

MPC9330

29

30

31

32

1

2

3

4

5

6

7

VCC_PLL

PWR_DN

CCLK

XTAL_IN

OE/MR

The MPC9330 requires an external RC filter for the analog power supply pin VCC_PLL. Please see application section for details.

Figure 2. MPC9330 32鈥揕ead Package Pinout

(Top View)

MOTOROLA

2

XTAL_OUT

NC

TIMING SOLUTIONS

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