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MPC9330数据手册封面

MPC9330 Datasheet

  • MPC9330

  • 3.3V 1:6 VLCMOS PLL Clock Generator

  • 136.03KB

  • Motorola   Motorola

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MPC9330
Table 7: AC CHARACTERISTICS
(VCC = 3.3V
卤
5%, TA = 鈥?0掳C to 85掳C)a b
Symbol
fref
Characteristics
Input Reference Frequencyc
PLL mode, external feedback
Min
50
25
16.67
12.5
8.33
12.5
200
10
梅
4 output
梅
8 output
梅
12 output
梅
16 output
梅
24 output
50
25
16.67
12.5
8.33
40
CCLK or PCLK to FB_IN
卤100
150
45
0.1
50
55
1.0
10
10
RMS (1
s
)i
RMS (1
s
)
RMS (1
s
)
梅
4 feedback
梅
8 feedback
梅
12 feedback
梅
16 feedback
梅
24 feedback
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Typ
Max
100
50
33.3
25
16.67
25
TBD
400
20
100
50
33.3
25
16.67
60
1.0
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
ns
ps
ps
%
ns
ns
ns
ps
ps
ps
kHz
kHz
kHz
kHz
kHz
0.55 to 2.4V
0.8 to 2.0V
FB_SEL=1 &
PLL locked
PLL locked
Condition
PLL locked
梅
4 feedbackd
梅
8 feedback
梅
12 feedback
梅
16 feedback
梅
24 feedback
PLL mode, internal feedback
鈱┟?/div>
16 feedback)
Input Reference Frequency in PLL bypass modee
VCO Lock Frequency Rangef
Crystal Interface Frequency Rangeg
Output Frequency
fVCO
fXTAL
fMAX
frefDC
tr, tf
t(鈭?
tsk(o)
DC
tr, tf
tPLZ, HZ
tPZL, LZ
tJIT(CC)
tJIT(PER)
tJIT(鈭?
BW
Reference Input Duty Cycle
CCLK Input Rise/Fall Time
Propagation Delay
(static phase offset)
Output-to-Output Skewh
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
I/O Phase Jitter
PLL closed loop bandwidthj
PLL mode, external feedback
a.
b.
c.
d.
e.
f.
g.
h.
i.
j.
tLOCK
Maximum PLL Lock Time
10
ms
All AC characteristics are design targets and subject to change upon device characterization.
AC characteristics apply for parallel output termination of 50鈩?to VTT.
PLL mode requires PLL_EN = 0 to enable the PLL.
梅4
feedback (FB) can be accomplished by setting PWR_DN = 0 and the connection of one
梅2
output to FB_IN. See Table 1 to Table 3 for
other feedback configurations.
In bypass mode, the MPC9330 divides the input reference clock.
The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO
梅
FB.
The usable crystal frequency range depends on the VCO lock frequency and the PLL feedback ratio.
See application section for part鈥搕o鈥損art skew calculation.
See application section for a jitter calculation for other confidence factors than 1
s
.
鈥? dB point of PLL transfer characteristics.
TIMING SOLUTIONS
5
MOTOROLA

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