您的位置：维库电子市场网 > Datasheet > CS5550

CS5550 Datasheet

  • CS5550

  • Two-channel, Low-cost A/D Converter

  • 536.00KB

  • 25页

  • CIRRUS

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

CS5550
5.5 OUT
1
and OUT
2
Output Registers
Address:
7
(AIN1
Output Register)
8 (AIN2 Output Register)
LSB
2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.....
2
-17
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
MSB
-(2
0
)
These signed registers contain the last value of the measured results of AIN1 and AIN2. The results will be with-
in the range of -1.0
鈮?/div>
AIN1,AIN2
<
1.0. The value is represented in two's complement notation, with the binary
point place to the right of the MSB (MSB has a negative weighting). These values are 22 bits in length. The two
least significant bits, (located at the far right-side) have no meaning, and will always have a value of 鈥?鈥?
5.6 FILT
1
, FILT
2
Unsigned Output Register
Address:
11
(AIN1
Filtered Output Register)
12 (AIN2 Filtered Output Register)
LSB
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
2
-8
.....
2
-18
2
-19
2
-20
2
-21
2
-22
2
-23
2
-24
MSB
2
-1
These unsigned registers contain the last values of FILT
1
and FILT
2
. The results are in the range of
0.0
鈮?/div>
FILT
1
,FILT
2
<
1.0. The value is represented in (unsigned) binary notation, with the binary point place to
the left of the MSB. These results are updated after each computation cycle.
5.7 Status Register and Mask Register
Address:
Address:
23
DRDY
15
7
15
(Status
[Clear] Register)
26 (Mask Register)
22
14
FOR1
6
21
13
FOR2
5
20
CRDY
12
4
OD2
19
11
3
OD1
18
10
2
17
OR1
9
1
16
OR2
8
0
IC
Default** = 0x000000 (Status [Clear] Register
0x000000 (Mask Register)
The Status [Clear] Register indicates the condition of the chip. In normal operation writing a '1' to a bit will cause
the bit to go to the '0' state. Writing a '0' to a bit will maintain the status bit in its current state. With this feature
the user can simply write back to the Status [Clear] Register to clear the bits that have been seen, without con-
cern of clearing any newly set bits. Even if a status bit is masked to prevent the interrupt (at the time that the
status bit is asserted), the status bit will still be set in (both of) the Status Registers so the user can poll the status.
The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in the Mask Register will
allow the corresponding bit in the Status Register to activate the INT pin when the status bit becomes active.
DRDY
Data Ready. When running in single or continuous conversion acquisition mode, this bit will in-
dicate the end of computation cycles. When running calibrations, this bit indicates that the cal-
ibration sequence has completed, and the results have been stored in the offset or gain
AIN Output Out of Range. Set when the
magnitude
of the calibrated output is too large or too
OR1, OR2
22
DS630F1

CS5550 PDF文件相关型号

CS5550-IS,CS5550-ISZ

CS5550相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！