CS5550
SWITCHING CHARACTERISTICS
Parameter
Master Clock Frequency
Internal Gate Oscillator (Note 7)
Master Clock Duty Cycle
CPUCLK Duty Cycle
(Note 8)
Rise Times
Any Digital Input Except SCLK
(Note 9)
SCLK
Any Digital Output
Fall Times
Any Digital Input Except SCLK
(Note 9)
SCLK
Any Digital Output
Start-up
Oscillator Start-Up Time
XTAL = 4.096 MHz (Note 10)
Serial Port Timing
Serial Clock Frequency
Serial Clock
SDI Timing
CS Falling to SCLK Rising
Data Set-up Time Prior to SCLK Rising
Data Hold Time After SCLK Rising
SCLK Falling Prior to CS Disable
SDO Timing
CS Falling to SDI Driving
SCLK Falling to New Data Bit (hold time)
CS Rising to SDO Hi-Z
Symbol
MCLK
Min
2.5
40
40
-
-
-
-
-
-
-
-
200
200
50
50
100
100
-
-
-
Typ
4.096
-
-
-
50
-
-
50
60
-
-
-
-
-
-
-
20
20
20
Max
5
60
60
1.0
100
-
1.0
100
-
-
2
-
-
-
-
-
-
50
50
50
Unit
MHz
%
%
碌s
碌s
ns
碌s
碌s
ns
ms
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
rise
t
fall
t
ost
SCLK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
Pulse Width High
Pulse Width Low
Notes: 7. Device parameters are specified with a 4.096 MHz clock. If a crystal is used, then XIN frequency must
remain between 2.5 MHz - 5.0 MHz.
8. If external MCLK is used, then its duty cycle must be between 45% and 55% to maintain this spec.
9. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
10. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
8
DS630F1