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DS2505数据手册封面

DS2505 Datasheet

  • DS2505

  • 16-kbit Add-Only Memory

  • 499.10KB

  • Dallas

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DS2505
protocol has been satisfied. This protocol is described in the ROM functions flow chart (Figure 8). The
1-Wire bus master must first provide one of four ROM function commands: 1) Read ROM, 2) Match
ROM, 3) Search ROM, or 4) Skip ROM. After a ROM function sequence has been successfully
executed, the bus master may then provide any one of the memory function commands specific to the
DS2505 (Figure 5).
The 1-Wire CRC of the lasered ROM is generated using the polynomial X
8
+ X
5
+ X
4
+ 1. Additional
information about the Dallas Semiconductor 1-Wire Cyclic Redundancy Check is available in the Book
of DS19xx iButton Standards. The shift register acting as the CRC accumulator is initialized to 0. Then
starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of
the family code has been entered, then the serial number is entered. After the 48
th
bit of the serial number
has been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC should return
the shift register to all zeroes.
DS2505 BLOCK DIAGRAM
Figure 1
3 of 24

DS2505 产品属性

  • 1

  • 集成电路 (IC)

  • 存储器

  • -

  • EPROMs

  • EPROM OTP

  • 16K（16K x 1）

  • -

  • 1 线 串行

  • -

  • -40°C ~ 85°C

  • TO-226-3、TO-92-3 标准主体

  • TO-92-3

  • 散装

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