PIC16C745 Datasheet

IC型号：
PIC16C745
PDF描述：
8-Bit CMOS Microcontrollers with USB
文件大小：
4945.69KB
PDF页数：
165页
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PIC16C745/765

9.3.1

PWM PERIOD

9.3.3

SET-UP FOR PWM OPERATION

The PWM period is specified by writing to the PR2 reg-

ister. The PWM period can be calculated using the fol-

lowing formula:

PWM period = [(PR2) + 1] 鈥?4 鈥?T

OSC

鈥?/div>

(TMR2 prescale value)

PWM frequency is defined as 1 / [PWM period].

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

鈥?TMR2 is cleared

鈥?The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin will not be set)

鈥?The PWM duty cycle is latched from CCPR1L into

CCPR1H

Note:

The Timer2 postscaler (see Section 8.1) is

not used in the determination of the PWM

frequency. The postscaler could be used to

have a servo update rate at a different fre-

quency than the PWM output.

PWM DUTY CYCLE

The following steps should be taken when configuring

the CCP module for PWM operation:

Set the PWM period by writing to the PR2 register.

Set the PWM duty cycle by writing to the

CCPR1L register and CCP1CON<5:4> bits.

Make the CCP1 pin an output by clearing the

TRISC<2> bit.

Set the TMR2 prescale value and enable Timer2

by writing to T2CON.

Configure the CCP1 module for PWM operation.

9.3.2

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available. The CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

PWM duty cycle = (CCPR1L:CCP1CON<5:4>) 鈥?/div>

Tosc 鈥?(TMR2 prescale value)

CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not latched into

CCPR1H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitchless PWM operation.

When the CCPR1H and 2-bit latch match TMR2 con-

catenated with an internal 2-bit Q clock or 2 bits of the

TMR2 prescaler, the CCP1 pin is cleared.

Maximum PWM resolution (bits) for a given PWM

frequency:

INT

log F

PWM

Resolution

(

)

bits

log(2)

Note:

If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not be

cleared.

漏

1999 Microchip Technology Inc.

Advanced Information

DS41124A-page 55

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