鈥?/div>
Routing of all I/O to any IA or MDAC
Any IA/MDAC summed to either output ampli铿乪r
Circuits with and without feedback possible
Routable to maintain pin location relationships
Single supply (+5V) operation
Precision voltage reference output (2.5V)
Power-down for
碌
Watt power consumption
Auto-calibration of internal offsets
Available in 28-pin PDIP or 24-pin SOIC
Recon铿乬urable or adaptive signal conditioning
Analog front end for most A/D converters
Programmable analog signal control loops
Precision programmable gain ampli铿乪rs
Auto-Calibration
2.5V Reference
2 PD
1 GND
ispPAC30 24-Pin SOIC
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Other Product Features
Description
The ispPAC
庐
30 is a member of the Lattice family of In-
System Programmable (ISP鈩? analog integrated cir-
cuits. It is digitally con铿乬ured via SRAM and utilizes
E
2
CMOS memory for non-volatile storage of its con铿乬u-
ration. The 铿俥xibility of ISP enables programming, veri铿?
cation and unlimited recon铿乬uration, directly on the
printed circuit board.
The ispPAC30 is a complete front end solution for data
acquisition applications using 10 to 12-bit ADC's. It pro-
vides multiple single-ended or differential signal inputs,
multiplexing, precision gain, offset adjustment, 铿乴tering,
and comparison functionality. It also has complete
routability of inputs or outputs to any input cell and then
from any input cell to either summing node of the two
output ampli铿乪rs. Designers con铿乬ure the ispPAC30
and verify its performance using PAC-Designer
庐
, an
easy to use, Microsoft Windows
庐
compatible develop-
ment tool. Device programming is supported using PC
parallel port I/O operations.
1
pac30_01
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Applications
Vin1
Vin2
Vin3
ispPAC30
Dual
12-Bit
ADC
碌Controller
www.latticesemi.com
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