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ISPPAC30-01PI Datasheet

  • ISPPAC30-01PI

  • Lattice Semiconductor [In-System Programmable Analog Circui...

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  • LATTICE   LATTICE

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Lattice Semiconductor
ispPAC30 Preliminary Data Sheet
In-System Programming
The ispPAC30 is an in-system programmable device. This is accomplished by integrating all E
2
con铿乬uration mem-
ory and SRAM control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial
JTAG interface at normal logic levels. Once a device is programmed, all con铿乬uration information is stored on-chip,
in non-volatile E
2
CMOS memory cells. The speci铿乧s of the IEEE 1149.1 serial interface and all ispPAC30 instruc-
tions are described in the JTAG interface section of this data sheet.
User Electronic Signature
A user electronic signature (UES) feature is included in the E
2
CMOS memory of the ispPAC30. This consists of 16
bits that can be con铿乬ured by the user to store unique data such as ID codes, revision numbers or inventory control
data. The speci铿乧s this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet.
Electronic Security
An electronic security 鈥渇use鈥?(ESF) bit is provided in every ispPAC30 device to prevent unauthorized readout of the
E
2
CMOS con铿乬uration bit patterns. Once programmed, this cell prevents further access to the functional user bits
in the device. This cell can only be erased by reprogramming the device, so the original con铿乬uration can not be
examined once programmed. Usage of this feature is optional. The speci铿乧s of this feature are discussed in the
IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a 铿乶al con铿乬uration is determined, an ASCII format JEDEC 铿乴e can be created using the PAC-Designer soft-
ware. Devices can then be ordered through the usual supply channels with the user鈥檚 speci铿乧 con铿乬uration already
preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and 铿俥xibility in production planning.
Evaluation Fixture
Included in the basic ispPAC30 Design Kit is an engineering prototype board that can be connected to the parallel
port of a PC using a Lattice download cable. It demonstrates proper layout techniques for the ispPAC30 and can be
used in real time to check circuit operation as part of the design process. Input and output connections as well as a
鈥渂readboard鈥?circuit area are provided to speed debugging of the circuit. This board is also useful as a program-
ming 铿亁ture for prototype and short production runs.
Figure 8. Download to a PC
PAC-Designer
Software
Other
System
Circuitry
ispDownload
Cable (6')
4
ispPAC30
Device
IEEE Standard 1149.1 Interface
Serial Port Programming Interface Communication with the ispPAC30 is facilitated via an IEEE 1149.1 test access
port (TAP). It is used by the ispPAC30 as a serial programming interface, and not for boundary scan test purposes.
24

ISPPAC30-01PI 产品属性

  • Lattice

  • SPLD - 简单可编程逻辑器件

  • ISPPA

  • 7 ns

  • 3 V to 3.6 V

  • + 85 C

  • - 40 C

  • PDIP-28

  • Through Hole

  • 13

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