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CS5321-BLZ Datasheet

  • CS5321-BLZ

  • Cirrus Logic [24-bit, Variable-bandwidth A/D Converter Chip...

  • 672.92KB

  • CIRRUS

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CS5321/22
2.8 Performance
Figure 22, 23 and 24 illustrate the spectral perfor-
mance of the CS5321/22 and chipset when operat-
ing from a 1.024 MHz master clock. Ten 1024
point FFTs were averaged to produce the plots.
Figure 22 illustrates the chip set with a 100 Hz,
-20 dB input signal. The sample rate was set at 1
kHz. Dynamic range is 122 dB.
The dynamic range calculated by the test soft-ware
is reduced somewhat in Figures 23 and 24 because
of jitter in the signal test oscillator. Jitter in the
100 Hz signal source is interpreted by the signal
processing software to be increased noise.
The choice of master clock frequency will affect
performance. The CS5321 will exhibit the best Sig-
nal to Distortion performance with slower modula-
tor sampling clock rates as slower sample rates
allow more time for amplifier settling.
For lowest offset drift, the CS5321 should be oper-
ated with MCLK = 1.024 MHz and HBR = 1. Slow-
er modulator sampling clock rates will exhibit
more offset drift. Changing MCLK to 512 kHz
(HBR = 1) or changing HBR to zero (MCLK =
1.024 MHz) will cause the drift rate to double. Off-
set drift is not linear over temperature so it is diffi-
cult to specify an exact drift rate. Offset drift
characteristics vary from part to part and will vary
as the power supply voltages vary. Therefore, if the
CS5321 is to be used in precision dc measurement
applications where offset drift is to be minimized,
the power supplies should be well regulated. The
CS5321 will exhibit about 6 ppm/掳C of offset drift
with MCLK = 1 and HBR = 1. Gain drift of the
CS5321 itself is about 5 ppm/掳C and is not affected
by either modulator sample rate or by power supply
variation.
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
0
500
Figure 22. 1024 Point FFT Plot with -20 dB Input, 100 Hz
Input, ten averages
D yn a m ic R a n g e = 1 2 2 .0 d B
HBR = 1
OFST = 0
LPW R = 0
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
0
500
see text
S /D = 1 1 6 .0 d B
S /N = 1 1 8 .4 d B
S /N + D = 1 1 4 .2 d B
HBR = 1
OFST = 0
LPW R = 0
Figure 23. 1024 Point FFT Plot with Full Scale Input,
100 Hz Input, HBR = 1, ten averages
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
0
500
see text
S /D = 1 2 2 .7 d B
S /N = 1 1 7 .1 d B
S /N + D = 1 1 6 .4 d B
HBR = 0
OFST = 0
LPW R = 0
Figure 24. 1024 Point FFT Plot with Full Scale Input,
100 Hz Input, HBR = 0, ten averages
22
DS454F2

CS5321-BLZ 产品属性

  • Cirrus Logic

  • ADC（模数转换器）

  • 1

  • 1

  • Delta-Sigma

  • 4 KSPs

  • 24 bit

  • Voltage

  • Serial

  • 115 dB

  • 4 V to 4.5 V

  • 4.75 V

  • 5.25 V

  • 100 mW

  • + 85 C

  • SMD/SMT

  • PLCC-28

  • Tube

  • - 55 C

  • +/- 4.5 V

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