CS5321/22
4. CS5322 PIN DESCRIPTIONS
CHIP SELECT
FRAME SYNC
CS
SYNC
R/W
RSEL
SCLK
SID
5
6
7
8
9
10
11
12 13 14 15 16 17 18
4
3
2
1
28 27 2 6 25
24
23
22
21
20
19
READ/WRITE
REGISTER SELECT
SERIAL CLOCK
SERIAL INPUT DATA
SERIAL OUTPUT DATA
DATA READY
POSITIVE DIGITAL POWER
DIGITAL GROUND
DECIMATION RATE CONTROL
DECIMATION RATE CONTROL
DECIMATION RATE CONTROL
CLOCK INPUT
CLKIN
RESET
RESET
MODULATOR SYNC
MSYNC
MODULATOR FLAG
MODULATOR CLOCK
POSITIVE DIGITAL POWER
DIGITAL GROUND
MFLG
MCLK
VD+
DGND
CS5322
TOP
VIEW
SOD
DRDY
VD+
DGND
DECA
DECB
DECC
ERROR
ERROR FLAG
MODULATOR DATA
MDATA
TEST DATA
TDATA
CHANNEL SELECT
HARDWARE/SOFTWARE MODE
CSEL
H/S
ORCAL
OFFSET CALIBRATION
POWER DOWN
PWDN
USEOR
USE OFFSET REGISTER
Power Supplies
VD+ 鈥?Positive Digital Power, Pin 8, 21
Positive digital supply voltage. Nominally +5 volts.
DGND 鈥?Digital Ground, Pin 9, 20
Digital ground reference.
Digital Outputs
MCLK 鈥?Modulator Clock Output, Pin 7
A CMOS-compatible clock output (nominally 1.024 MHz) that provides the necessary clock for
operation of the modulator.
MSYNC 鈥?Modulator Sync, Pin 5
The transition from a low to high level on this output will re-initialize the CS5321.
ERROR - Error Flag, Pin 23
This signal is the output of an open pull-up NOR gate with a nominal 100 k鈩?pull-up resistor
to which the error status data (OVERWRITE error, MFLG error, ACC1 error and ACC2 error)
are inputs. When low, it notifies the host processor that an error condition exists. The ERROR
signal can be wire OR鈥檇 together with other filters鈥?outputs. The value of the internal pull-up
resistor is 100 k鈩?
DRDY - Data Ready, Pin 22
When high, data is ready to be shifted out of the serial port data register.
DS454F2
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