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CS5510-AS Datasheet

  • CS5510-AS

  • Cirrus Logic [16-bit and 20-bit, 8-pin Sigma-Delta ADC]

  • 429.30KB

  • CIRRUS

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CS5510/11/12/13
Bipolar Input Voltage
>(VFS-1.5 LSB)
VFS-1.5 LSB
Two's Complement (20-Bit)
7FFFF
7FFFF
-----
7FFFE
00000
-----
FFFFF
80001
-----
80000
Two's Complement (16-Bit)
7FFF
7FFF
-----
7FFE
0000
-----
FFFF
8001
-----
8000
-0.5 LSB
-VFS+0.5 LSB
Note: VFS in the table equals the voltage between AIN+ and AIN-. See text about error flags
under overrange conditions.
Table 3. CS5510/11/12/13 Output Coding.
cessively overranged. If the OD bit is set, the con-
version data bits can be completely erroneous. The
OD flag bit will be cleared to logic 0 four output
words after the modulator becomes stable again.
The OD flag can occur independent of OF with a
spike on the input. Both flag bits should be tested
if any overrange condition occurs.
Table 3 illustrates the output coding for the
CS5510/11/12/13. Conversions are output as
two's complement values representing bipolar in-
put signals.
2.5.4
Digital Filter
The CS5510/11/12/13 have a modified Sinc
4
digi-
tal filter that provides CLK/612 Hz conversion rates
(CLK represents SCLK for the CS5510/12 and the
internal oscillator for the CS5511/13). The filters
are optimized to yield better than 80 dB rejection
between 47 Hz to 63 Hz (i.e. 80 dB minimum rejec-
tion for both 50 Hz and 60 Hz) when the master
clock is 32.768 kHz. The filter has a response as
shown in Figure 20. Table 4 shows the filter re-
sponse for frequencies from 38 Hz to 71 Hz. Note
that the response of the CS5511/13 will be similar,
but the frequencies scale with the on-chip oscilla-
tor鈥檚 frequency, which can be from 32 kHz to
96 kHz (i.e. conversion rates can vary between
53 Sps to 159 Sps). Further note that after initial
power up, or after returning from sleep mode, the
filter requires four conversion cycles to produce a
D23
0
D11
11
D22
OF
D10
10
D21
OD
D9
9
D20
0
D8
8
D19
MSB
D7
7
D18
18
D6
6
D17
17
D5
5
D16
16
D4
4
D15
15
D3
3
D14
14
D2
2
D13
13
D1
1
D12
12
D0
LSB
Table 1. CS5512/13 Output Conversion Data Register Description (Flags + 20 bits).
D23
0
D11
11
D22
OF
D10
10
D21
OD
D9
9
D20
0
D8
8
D19
0
D7
7
D18
0
D6
6
D17
0
D5
5
D16
0
D4
4
D15
MSB
D3
3
D14
14
D2
2
D13
13
D1
1
D12
12
D0
LSB
Table 2. CS5510/11 Output Conversion Data Register Description (Flags + 16 bits).
18
DS337F3

CS5510-AS PDF文件相关型号

CS5510-ASZ,CS5511-AS,CS5511-ASZ,CS5512-BS

CS5510-AS 产品属性

  • Cirrus Logic

  • ADC（模数转换器）

  • Delta-Sigma

  • 0.0535 KSPs

  • Voltage

  • 400 mW

  • + 85 C

  • SMD/SMT

  • SOIC-8

  • Tube

  • - 40 C

  • 100

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