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CS5510-AS Datasheet

  • CS5510-AS

  • Cirrus Logic [16-bit and 20-bit, 8-pin Sigma-Delta ADC]

  • 429.30KB

  • CIRRUS

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CS5510/11/12/13
0
-20
-40
CS5510/12
SCLK = 32.768 kHz
Magnitude (dB)
-60
-80
-100
47 Hz
-120
-140
0
20
40
60
63 Hz
80
100
120
Frequency (Hz)
Figure 20. Digital Filter Response.
Frequency
(Hz)
38
39
40
41
42
43
44
45
46
Rejection
(dB)
37
39
42
46
49
54
58
64
72
Frequency
(Hz)
47
48
49
50
51
52
53
54
55
Rejection
(dB)
84
92
88
92
105
89
86
85
87
Frequency
(Hz)
56
57
58
59
60
61
62
63
64
Rejection
(dB)
91
109
94
89
88
92
104
84
77
Frequency
(Hz)
65
66
67
68
69
70
71
-
-
Rejection
(dB)
73
69
66
64
63
61
60
-
-
Table 4. Digital Filter Response at 32.768 kHz.
valid conversion due to the modified Sinc
4
filter
characteristics.
2.5.5
Multiplexed Applications
The settling performance of the CS5510/11/12/13
in multiplexed applications is determined by the
Sinc
4
filter. To settle, a step input requires 4 full
conversion cycles after the analog input has
switched. In this case, the throughput is reduced
by a factor of four as the first three conversions af-
ter the step is applied will not be fully settled.
If the application does not require the maximum
throughput possible from the ADC, the multiplexer
can be switched at any time. In this case, the sys-
tem must wait for at least five conversion cycles for
a fully-settled result from the ADC.
If maximum throughput is required in a multiplexed
application, the multiplexer must be switched at the
correct time during the data collection process. For
maximum throughput with the CS5510/12, switch-
ing of a multiplexer should occur 595 SCLK cycles
after SDO falls. For maximum throughput with the
CS5511/13, switching of a multiplexer should oc-
cur on the rising edge of SDO during a conversion
in which the data word is not read. The conversion
data that is immediately available when SDO falls
again is valid, and represents the analog input from
the previous multiplexer setting. The next three
conversions from the part will be unsettled values,
and the fourth conversion will represent a fully-set-
tled result from the new multiplexer setting. The
multiplexer should be switched again at the appro-
DS337F3
19

CS5510-AS PDF文件相关型号

CS5510-ASZ,CS5511-AS,CS5511-ASZ,CS5512-BS

CS5510-AS 产品属性

  • Cirrus Logic

  • ADC（模数转换器）

  • Delta-Sigma

  • 0.0535 KSPs

  • Voltage

  • 400 mW

  • + 85 C

  • SMD/SMT

  • SOIC-8

  • Tube

  • - 40 C

  • 100

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