3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
MAX793/MAX794/MAX795
PMOS FET
BODY DIODE
3.0V OR 3.3V
TO CMOS RAM
D
G
V
CC
BATT ON
OUT
V
CC
BATT ON
OUT
S
MAX793
MAX794
MAX795
MAX793
MAX794
MAX795
GND
GND
(a)
(b)
Figure 14. Driving an External Transistor with BATT ON
3.0V OR 3.3V
+5V
V
CC
1N4148
BATT
0.47F
MAX793
MAX794
OUT
V
CC
TO STATIC
RAM
3.0V OR
3.3V
1N4148
V
CC
MAX793
MAX794
OUT
V
CC
TO STATIC
RAM
RESET
TO
碌P
0.47F
BATT
RESET
TO
碌P
GND
GND
(a)
(b)
Figure 15. Using a SuperCap鈩?as a Backup Source
____________________________Erratum
Initial versions of the MAX793 and MAX794 have a
logic design error that can cause the loss of output volt-
age (OUT) when V
CC
is absent even though a backup
battery is connected to the BATT input. Applications
that do not use the MR input (including all MAX795
applications) are unaffected by this phenomenon.
Also, applications that do not use PFO are unaffected if
PFI is tied to V
CC
.
The loss of output voltage is caused by the IC incor-
rectly entering the battery 鈥渇reshness seal鈥?mode.
Normally, freshness seal mode is activated by ground-
ing PFO during a power-up reset timeout period. Then,
the removal of V
CC
powers the IC down without con-
necting the backup battery to OUT.
16
The IC decides whether or not to enter freshness seal
mode during all reset timeout periods. During a power-
up reset timeout period (which occurs when V
CC
is
raised above the MAX793鈥檚 reset threshold or the volt-
age on the MAX794鈥檚 RESET IN pin is raised above the
RESET IN threshold), the IC momentarily disconnects
the PFO pin from the comparator output and lightly
pulls PFO up to V
CC
. The voltage level on the PFO pin
is then tested and, if it is low, freshness seal mode is
chosen. (PFO is reconnected to the comparator output
before the end of the reset timeout period.)
However, when a reset is initiated by MR, the PFO pin
incorrectly remains connected to the comparator output
during the entire timeout period and is not pulled up. If
the comparator is driving PFO low during an MR reset
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