MAX793T Datasheet

  • MAX793T

  • 3.0V/3.3V可调、微处理器监控电路, 微处理器监控电路, 提供备用...

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3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
______________________________________________________________Pin Description
PIN
MAX793/
MAX794
NAME
MAX795
Supply Output for CMOS RAM. When V
CC
rises above the reset threshold or above
V
BATT
, OUT is connected to V
CC
through an internal P-channel MOSFET switch. When
V
CC
falls below V
SW
and V
BATT
, BATT connects to OUT.
Main Supply Input
Battery Status Output. High in normal operating mode when V
BATT
exceeds V
BOK
, other-
wise low. V
BATT
is checked continuously. Disabled and logic low while V
CC
is below V
SW
.
Reset Input. Connect to an external resistor divider to select the reset threshold. The
reset threshold can be programmed anywhere in the V
SW
to 5.5V range.
Power-Fail Comparator Input. When PFI is less than V
PFT
or when V
CC
falls below V
SW
,
PFO goes low; otherwise, PFO remains high (see
Power-Fail Comparator
section).
Connect to V
CC
if unused.
Logic Output/External Bypass Switch-Driver Output. High when OUT switches to BATT.
Low when OUT switches to V
CC
. Connect the base/gate of PNP/PMOS transistor to
BATT ON for I
OUT
requirements exceeding 75mA.
Ground
Power-Fail Comparator Output. When PFI is less than V
PFT
or when V
CC
falls below
V
SW
, PFO goes low; otherwise, PFO remains high. PFO is also used to enable the bat-
tery freshness seal (see Battery
Freshness Seal,
and
Power-Fail Comparator
sections).
Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as
MR is low and for 200ms after MR returns high. The active-low input has an internal
70碌A pull-up current. In can be driven from a TTL- or CMOS-logic line or shorted to
ground with a switch. Leave open if unused.
Watchdog Output. WDO goes low if WDI remains either high or low for longer than the
watchdog timeout period. WDO returns high on the next transition of WDI. WDO is a
logic high for V
SW
< V
CC
< V
RST
, and low when V
CC
is below V
SW
.
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout
period, the internal watchdog timer runs out and WDO goes low. WDO returns high on
the next transition of WDI. Connect WDO to MR to generate a reset due to a watchdog
fault.
Chip-Enable Input. The input to the chip-enable gating circuit. Connect to GND if unused
Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted.
If CE IN is low when reset is asserted, CE OUT will remain low for 10碌s or until CE IN
goes high, whichever occurs first. CE OUT is pulled up to OUT.
Active-High Reset Output. Sources and sinks current. RESET is the inverse of RESET.
Early Power-Fail Warning Output. Low when V
CC
falls to V
LR
. This output can be used to
generate an NMI to provide early warning of imminent power-failure.
Open-Drain, Active-Low Reset Output. Pulses low for 200ms when triggered, and stays
low whenever V
CC
is below the reset threshold or when MR is a logic low. It remains low
for 200ms after either V
CC
rises above the reset threshold, the watchdog triggers a reset
(WDO connected to MR), or MR goes low to high.
Backup-Battery Input. When V
CC
falls below V
SW
and V
BATT
, OUT switches from V
CC
to
BATT. When V
CC
rises above the reset threshold or above V
BATT
, OUT reconnects to
V
CC
. V
BATT
may exceed V
CC
. Connect V
CC
, OUT, and BATT together if no battery is
used.
7
FUNCTION
MAX793/MAX794/MAX795
1
2
1
2
OUT
V
CC
BATT OK
(MAX793)
3
鈥?/div>
RESET IN
(MAX794)
4
鈥?/div>
PFI
5
6
7
3
4
鈥?/div>
BATT ON
GND
PFO
8
鈥?/div>
MR
9
鈥?/div>
WDO
10
11
12
13
14
鈥?/div>
5
6
鈥?/div>
鈥?/div>
WDI
CE IN
CE OUT
RESET
LOWLINE
15
7
RESET
16
8
BATT
_______________________________________________________________________________________

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