MPC885 Datasheet

  • MPC885

  • Freescale Semiconductor, Inc [Hardware Specifications]

  • 1498.97KB

  • FREESCALE

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Bus Signal Timing
Table 9. Bus Operation Timings (continued)
33 MHz
Num
Characteristic
Min
B42
B43
1
For
40 MHz
Min
2.00
鈥?/div>
Max
鈥?/div>
TBD
66 MHz
Min
2.00
鈥?/div>
Max
鈥?/div>
TBD
80 MHz
Unit
Min
2.00
鈥?/div>
Max
鈥?/div>
TBD
ns
ns
Max
鈥?/div>
TBD
CLKOUT rising edge to TS valid (hold
time) (MIN = 0.00
B1 + 2.00)
AS negation to memory controller signals
negation (MAX = TBD)
2.00
鈥?/div>
part speeds above 50 MHz, use 9.80 ns for B11a.
timing required for BR input is relevant when the MPC885/880 is selected to work with the internal bus arbiter.
The timing for BG input is relevant when the MPC885/880 is selected to work with the external bus arbiter.
3
For part speeds above 50 MHz, use 2 ns for B17.
4
The D(0:31) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is asserted.
5
For part speeds above 50 MHz, use 2 ns for B19.
6
The D(0:31) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read
accesses controlled by chip-selects under control of the user-programmable machine (UPM) in the memory
controller, for data beats where DLT3 = 1 in the RAM words. (This is only the case where data is latched on the falling
edge of CLKOUT.)
7
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
8
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in
B37 and B38 are specified to enable the freeze of the UPM output signals as described in
Figure 20.
9
The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior
specified in
Figure 23.
2
The
MPC885/MPC880 Hardware Specifications, Rev. 3
23
Freescale Semiconductor

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