UTOPIA AC Electrical Specifications
Table 32. UTOPIA Slave (Split Bus Mode) Electrical Specifications
Num
U1
Signal Characteristic
UtpClk rise/fall time (external clock option)
Duty cycle
Frequency
U2
U3
U4
UTPB, SOC, Rxclav and Txclav active delay
UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr setup
time
UTPB_AUX, SOC_Aux, RxEnb, TxEnb, RxAddr, and TxAddr hold
time
Output
Input
Input
2 ns
4 ns
1 ns
Direction
Input
40
Min
Max
4 ns
60
33
16 ns
Unit
ns
%
MHz
ns
ns
ns
Figure 70
shows signal timings during UTOPIA receive operations.
U1
UtpClk
U2
PHREQn
U3
3
RxClav
High-Z at MPHY
U2
2
U1
U4
4
High-Z at MPHY
RxEnb
UTPB
SOC
U3
3
U4
4
Figure 70. UTOPIA Receive Timing
MPC885/MPC880 Hardware Specifications, Rev. 3
70
Freescale Semiconductor