鈥?/div>
鈥?Advanced encryption standard unit (AESU)
鈥?Implements the Rinjdael symmetric key cipher
鈥?ECB, CBC, and counter modes
鈥?128-, 192-, and 256- bit key lengths
鈥?Message digest execution unit (MDEU)
鈥?SHA with 160- or 256-bit message digest
鈥?MD5 with 128-bit message digest
鈥?HMAC with either algorithm
鈥?Crypto-channel supporting multi-command descriptor chains
鈥?Integrated controller managing internal resources and bus mastering
鈥?Buffer size of 256 bytes for the DEU, AESU, and MDEU, with flow control for large data sizes
Interrupts
鈥?Six external interrupt request (IRQ) lines
鈥?12 port pins with interrupt capability
鈥?23 internal interrupt sources
鈥?Programmable priority between SCCs
鈥?Programmable highest priority request
Communications processor module (CPM)
鈥?RISC controller
鈥?Communication-specific commands (for example,
GRACEFUL STOP TRANSMIT
,
ENTER HUNT MODE
, and
RESTART TRANSMIT
)
鈥?Supports continuous mode transmission and reception on all serial channels
鈥?8-Kbytes of dual-port RAM
鈥?Several serial DMA (SDMA) channels to support the CPM
鈥?Three parallel I/O registers with open-drain capability
On-chip 16
脳
16 multiply accumulate controller (MAC)
鈥?One operation per clock (two-clock latency, one-clock blockage)
鈥?MAC operates concurrently with other instructions
鈥?FIR loop鈥擣our clocks per four multiplies
Four baud rate generators
鈥?Independent (can be connected to any SCC or SMC)
鈥?Allow changes during operation
鈥?Autobaud support option
Up to three serial communication controllers (SCCs) supporting the following protocols:
鈥?Serial ATM capability on SCCs
鈥?Optional UTOPIA port on SCC4
鈥?Ethernet/IEEE 802.3 optional on the SCC(s) supporting full 10-Mbps operation
鈥?HDLC/SDLC
鈥?HDLC bus (implements an HDLC-based local area network (LAN))
鈥?Asynchronous HDLC to support point-to-point protocol (PPP)
MPC885/MPC880 Hardware Specifications, Rev. 3
4
Freescale Semiconductor