Bus Signal Timing
Table 13
shows the debug port timing for the MPC885/880.
Table 13. Debug Port Timing
All Frequencies
Num
Characteristic
Min
D61
D62
D63
D64
D65
D66
D67
DSCK cycle time
DSCK clock pulse width
DSCK rise and fall times
DSDI input data setup time
DSDI data hold time
DSCK low to DSDO data valid
DSCK low to DSDO invalid
3
脳
T
CLOCKO
UT
Unit
Max
-
-
3.00
ns
ns
ns
15.00
2.00
ns
ns
1.25
脳
T
CLO
CKOUT
0.00
8.00
5.00
0.00
0.00
Figure 32
provides the input timing for the debug port clock.
DSCK
D61
D61
D63
D62
D62
D63
Figure 32. Debug Port Clock Input Timing
Figure 33
provides the timing for the debug port.
DSCK
D64
D65
DSDI
D66
D67
DSDO
Figure 33. Debug Port Timings
MPC885/MPC880 Hardware Specifications, Rev. 3
41
Freescale Semiconductor