鈥?/div>
ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2/1.
is asserted whenever the SDMA writes the incoming frame DA into memory.
CLSN(CTS1)
(Input)
120
Figure 61. Ethernet Collision Timing Diagram
RCLK1
121
124
RxD1
(Input)
125
126
127
RENA(CD1)
(Input)
121
123
Last Bit
Figure 62. Ethernet Receive Timing Diagram
MPC885/MPC880 Hardware Specifications, Rev. 3
62
Freescale Semiconductor