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K9K4G08U0M Datasheet

  • K9K4G08U0M

  • Samsung semiconductor [512M x 8 Bit / 256M x 16 Bit NAND Fl...

  • 600.21KB

  • SAMSUNG

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K9W8G08U1M
K9K4G08Q0M
K9K4G08U0M
VALID BLOCK
K9K4G16Q0M
K9K4G16U0M
Parameter
Symbol
N
VB
N
VB
Min
4016
8032*
FLASH MEMORY
Max
4096
8192*
Unit
Blocks
Blocks
K9K4GXXX0M
K9W8G08U1M
Valid Block Number
Valid Block Number
NOTE
:
1. The
device
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
. Do not erase or pro-
gram factory-marked bad blocks.
Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase
cycles.
* :
Each K9K4G08U0M chip in the K9W8G08U1M has Maximum 80 invalid blocks.
AC TEST CONDITION
(K9XXGXXUXM-XCB0 :TA=0 to 70掳C, K9XXGXXUXM-XIB0:TA=-40 to 85掳C
K9K4GXXQ0M : Vcc=1.70V~1.95V , K9XXGXXUXM : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
K9K4GXXQ0M:Output Load (Vcc:1.8V +/-10%)
K9XXGXXUXM:Output Load (Vcc:3.0V +/-10%)
K9K4GXXQ0M
0V to Vcc
5ns
Vcc/2
1 TTL GATE and CL=30pF
K9XXGXXUXM
0V to Vcc
5ns
Vcc/2
1 TTL GATE and CL=50pF
CAPACITANCE
(
T
A
=25掳C, V
CC
=1.8V/3.3V, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
C
I/O
C
IN
Test Condition
V
IL
=0V
V
IN
=0V
Max
K9XXGXXXXM
20
20
K9W8G08U1M
40
40
Unit
pF
pF
NOTE
: Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
H
L
L
L
X
X
X
X
X
ALE
L
H
L
H
L
L
X
X
X
X
(1)
X
CE
L
L
L
L
L
L
X
X
X
X
H
H
X
X
X
X
X
H
X
X
X
X
WE
RE
H
H
H
H
H
WP
X
X
H
H
H
X
X
H
H
L
0V/V
CC
(2)
PRE
X
X
X
X
X
X
X
X
X
X
0V/V
CC
(2)
Data Input
Data Output
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
Stand-by
Write Mode
Read Mode
Mode
Command Input
Address Input(5clock)
Command Input
Address Input(5clock)
NOTE
: 1. X can be V
IL
or V
IH.
2. WP and PRE should be biased to CMOS high or CMOS low for standby.
10

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