K9W8G08U1M
K9K4G08Q0M
K9K4G08U0M
K9K4G16Q0M
K9K4G16U0M
FLASH MEMORY
Figure 1-2. K9XXG16XXM (X16) Functional Block Diagram
V
CC
V
SS
A
11
- A
28
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
4096M + 128M Bit
NAND Flash
ARRAY
(1024 + 32)Word x 262144
Data Register & S/A
Cache Register
Y-Gating
Command
Command
Register
I/O Buffers & Latches
V
CC
V
SS
I/0 0
A
0
- A
10
CE
RE
WE
Control Logic
& High Voltage
Generator
Global Buffers
Output
Driver
I/0 15
CLE ALE PRE WP
Figure 2-2. K9XXG16XXM (X16) Array Organization
1 Block = 64 Pages
(64K + 2k) Word
256K Pages
(=4,096 Blocks)
16 bit
1K Words
32 Words
1 Page = (1K + 32)Words
1 Block = (1K + 32)Word x 64 Pages
= (64K + 2K) Words
1 Device = (1K+32)Word x 64Pages x 4096 Blocks
= 4224 Mbits
Page Register
1K Words
32 Words
I/O 3
A
3
*L
A
14
A
22
*L
I/O 4
A
4
*L
A
15
A
23
*L
I/O 0 ~ I/O 15
I/O 0
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
A
0
A
8
A
11
A
19
A
27
I/O 1
A
1
A
9
A
12
A
20
A
28
I/O 2
A
2
A
10
A
13
A
21
*L
I/O 5
A
5
*L
A
16
A
24
*L
I/O 6
A
6
*L
A
17
A
25
*L
I/O 7
A
7
*L
A
18
A
26
*L
I/O8 ~ 15
*L
*L
*L
*L
*L
Column Address
Column Address
Row Address
Row Address
Row Address
NOTE
: Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
7