PIC16C717/770/771
7.2
Timer2 Interrupt
FIGURE 7-1:
Sets flag
bit TMR2IF
TIMER2 BLOCK DIAGRAM
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is ini-
tialized to FFh upon reset.
TMR2
output
(1)
Reset
Prescaler
1:1, 1:4, 1:16
2
TMR2 reg
Comparator
F
OSC
/4
7.3
Output of TMR2
Postscaler
1:1 to 1:16
4
EQ
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate shift clock.
PR2 reg
Note 1:
TMR2 register output can be software selected
by the SSP Module as a baud clock.
TABLE 7-1:
Address
Name
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7
GIE
鈥?/div>
鈥?/div>
Timer2 register
鈥?/div>
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1
Bit 6
PEIE
ADIF
ADIE
Bit 5
T0IE
鈥?/div>
鈥?/div>
Bit 4
INTE
鈥?/div>
鈥?/div>
Bit 3
RBIE
SSPIF
SSPIE
Bit 2
T0IF
CCP1IF
CCP1IE
Bit 1
INTF
TMR2IF
TMR2IE
Bit 0
RBIF
TMR1IF
TMR1IE
Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh,
INTCON
10Bh,18Bh
0Ch
8Ch
11h
12h
92h
PIR1
PIE1
TMR2
T2CON
PR2
0000 000x 0000 000u
-0-- 0000 -0-- 0000
-0-- 0000 -0-- 0000
0000 0000 0000 0000
T2CKPS0
-000 0000 -000 0000
1111 1111 1111 1111
Timer2 Period Register
Legend:
x
= unknown,
u
= unchanged,
-
= unimplemented read as 鈥?鈥? Shaded cells are not used by the Timer2 module.
DS41120A-page 54
Advanced Information
漏
1999 Microchip Technology Inc.
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