PIC16C770 Datasheet

IC型号：
PIC16C770
PDF描述：
18/20-Pin, 8-Bit CMOS Microcontrollers with 10/12-bit A/D
文件大小：
3585.57KB
PDF页数：
220页
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PIC16C717/770/771

determine when the transmission/reception has com-

pleted. The SSPBUF must be read and/or written. If the

interrupt method is not going to be used, then software

polling can be done to ensure that a write collision does

not occur.

Example 9-1

shows the loading of the

SSPBUF (SSPSR) for data transmission.

SDI, SDO, SCK and SS pins as serial port pins. For the

pins to behave as the serial port function, some must

have their data direction bits (in the TRIS register)

appropriately programmed. That is:

鈥?/div>

SDI is automatically controlled by the SPI module

SDO must have TRISB<5> cleared

SCK (Master mode) must have TRISB<2> cleared

SCK (Slave mode) must have TRISB<2> set

SS must have TRISB<1> set, and ANSEL<5>

cleared

EXAMPLE 9-1:

LOADING THE SSPBUF

(SSPSR) REGISTER

;Specify Bank 1

;Has data been

;received

;(transmit

;complete)?

;No

;Specify Bank 0

;W reg = contents

;of SSPBUF

;Save in user RAM

;W reg = contents

; of TXDATA

;New data to xmit

BSF

STATUS, RP0

LOOP BTFSS SSPSTAT, BF

GOTO

BCF

MOVF

LOOP

STATUS, RP0

SSPBUF, W

Any serial port function that is not desired may be over-

ridden by programming the corresponding data direc-

tion (TRIS) register to the opposite value.

9.1.3

TYPICAL CONNECTION

MOVWF RXDATA

MOVF TXDATA, W

MOVWF SSPBUF

The SSPSR is not directly readable or writable, and can

only be accessed by addressing the SSPBUF register.

Additionally, the MSSP status register (SSPSTAT) indi-

cates the various status conditions.

9.1.2

ENABLING SPI I/O

Figure 9-2

shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their pro-

grammed clock edge, and latched on the opposite edge

of the clock. Both processors should be programmed to

same Clock Polarity (CKP), then both controllers would

send and receive data at the same time. Whether the

data is meaningful (or dummy data) depends on the

application software. This leads to three scenarios for

data transmission:

鈥?Master sends data 鈥?Slave sends dummy data

鈥?Master sends data 鈥?Slave sends data

鈥?Master sends dummy data 鈥?Slave sends data

To enable the serial port, MSSP Enable bit, SSPEN

(SSPCON<5>) must be set. To reset or reconfigure SPI

mode, clear bit SSPEN, re-initialize the SSPCON reg-

isters, and then set bit SSPEN. This configures the

FIGURE 9-2:

SPI MASTER/SLAVE CONNECTION

SPI Master SSPM<3:0> = 00xxb

SDO

SDI

SPI Slave SSPM<3:0> = 010xb

Serial Input Buffer

(SSPBUF)

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb

LSb

SDI

SDO

Shift Register

(SSPSR)

MSb

LSb

SCK

PROCESSOR 1

Serial Clock

SCK

PROCESSOR 2

DS41120A-page 72

Advanced Information

漏

1999 Microchip Technology Inc.

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