漏
1999 Microchip Technology Inc.
Write to SSPCON2<4>
to start acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
Master configured as a receiver
by programming SSPCON2<3>, (RCEN = 1)
RCEN cleared
automatically
Receiving Data from Slave
D0
ACK
D7 D6 D5 D4 D3 D2 D1
D0
ACK
ACK is not sent
3
4
5
1
2
3
4
5
1
2
3
4
8
9
6
7
8
9
6
7
5
6
7
8
9
P
Bus Master
terminates
transfer
Receiving Data from Slave
D7 D6 D5 D4 D3 D2 D1
RCEN = 1 start
next receive
RCEN cleared
automatically
ACK from Master
SDA = ACKDT = 0
Set ACKEN start acknowledge sequence
SDA = ACKDT = 1
PEN bit = 1
written here
Data shifted in on falling edge of CLK Set SSPIF at end
of receive
Set SSPIF interrupt
at end of receive
Set SSPIF interrupt
at end of acknowledge
sequence
Cleared in software
Cleared in
software
Cleared in software
Cleared in software
Set P bit
(SSPSTAT<4>)
and SSPIF
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPOV is set because
SSPBUF is still full
Write to SSPCON2<0>, (SEN = 1)
Begin Start Condition
SEN = 0
Write to SSPBUF occurs here
ACK from Slave
Start XMIT
SDA
Transmit Address to Slave R/W = 1
A7 A6 A5 A4 A3 A2 A1
ACK
SCL
S
1
2
Set SSPIF interrupt
at end of acknow-
ledge sequence
SSPIF
FIGURE 9-25: I
2
C MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS)
Advanced Information
SDA = 0, SCL = 1
while CPU
responds to SSPIF
Cleared in software
BF
(SSPSTAT<0>)
SSPOV
PIC16C717/770/771
ACKEN
DS41120A-page 97