PIC16C770 Datasheet

IC型号：
PIC16C770
PDF描述：
18/20-Pin, 8-Bit CMOS Microcontrollers with 10/12-bit A/D
文件大小：
3585.57KB
PDF页数：
220页
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PIC16C717/770/771

9.1.7

SLEEP OPERATION

9.1.8

EFFECTS OF A RESET

In master mode, all module clocks are halted and the

transmission/reception will remain in that state until the

device wakes from sleep. After the device returns to

normal mode, the module will continue to transmit/

receive data.

In slave mode, the SPI transmit/receive shift register

operates asynchronously to the device. This allows the

device to be placed in sleep mode and data to be

shifted into the SPI transmit/receive shift register.

When all 8 bits have been received, the MSSP interrupt

flag bit will be set and if enabled will wake the device

from sleep.

A reset disables the MSSP module and terminates the

current transfer.

TABLE 9-1:

Address

0Bh, 8Bh,

10Bh,18Bh

0Ch

8Ch

13h

14h

94h

REGISTERS ASSOCIATED WITH SPI OPERATION

Name

INTCON

PIR1

PIE1

SSPBUF

SSPCON

SSPSTAT

WCOL

SMP

Bit 7

GIE

鈥?/div>

Bit 6

PEIE

ADIF

ADIE

Bit 5

T0IE

鈥?/div>

Bit 4

INTE

鈥?/div>

Bit 3

RBIE

SSPIF

SSPIE

Bit 2

T0IF

CCP1IF

CCP1IE

Bit 1

INTF

TMR2IF

TMR2IE

Bit 0

RBIF

TMR1IF

TMR1IE

POR, BOR

0000 000x

-0-- 0000

xxxx xxxx

SSPM0

0000 0000

MCLR, WDT

0000 000u

-0-- 0000

uuuu uuuu

0000 0000

Synchronous Serial Port Receive Buffer/Transmit Register

SSPOV

CKE

SSPEN

D/A

CKP

SSPM3

SSPM2

R/W

SSPM1

Legend:

= unknown,

= unchanged,

= unimplemented read as 鈥?鈥? Shaded cells are not used by the MSSP in SPI mode.

DS41120A-page 76

Advanced Information

漏

1999 Microchip Technology Inc.

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