PIC16F87X Datasheet

IC型号：
PIC16F87X
PDF描述：
28/40-pin 8-Bit CMOS FLASH Microcontrollers
文件大小：
1377.31KB
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PIC16F87X

4.8

4.8.1

Protection Against Spurious Write

EEPROM DATA MEMORY

4.9

Operation during Code Protect

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, the WREN bit is cleared.

Also, the Power-up Timer (72 ms duration) prevents

EEPROM write.

The write initiate sequence and the WREN bit together

help prevent an accidental write during brown-out,

power glitch, or software malfunction.

4.8.2

PROGRAM FLASH MEMORY

Each reprogrammable memory block has its own code

protect mechanism. External Read and Write opera-

tions are disabled if either of these mechanisms are

enabled.

4.9.1

DATA EEPROM MEMORY

The microcontroller itself can both read and write to the

internal Data EEPROM, regardless of the state of the

code protect configuration bit.

4.9.2

PROGRAM FLASH MEMORY

To protect against spurious writes to FLASH program

memory, the WRT bit in the configuration word may be

programmed to 鈥?鈥?to prevent writes. The write initiate

sequence must also be followed. WRT and the config-

uration word cannot be programmed by user code, only

through the use of an external programmer.

The microcontroller can read and execute instructions

out of the internal FLASH program memory, regardless

of the state of the code protect configuration bits. How-

ever the WRT configuration bit and the code protect bits

have different effects on writing to program memory.

Table 4-1 shows the various configurations and status

of reads and writes. To erase the WRT or code protec-

tion bits in the configuration word requires that the

device be fully erased.

TABLE 4-1:

READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY

Memory Location

Internal

Read

Yes

Internal

Write

Yes

ICSP Read ICSP Write

Yes

Configuration Bits

CP1

CP0

WRT

All program memory

Unprotected areas

Protected areas

Unprotected areas

Protected areas

Unprotected areas

Protected areas

Unprotected areas

Protected areas

All program memory

TABLE 4-2:

Address

REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH

Bit 7

GIE

Name

Bit 6

PEIE

Bit 5

T0IE

Bit 4

INTE

Bit 3

RBIE

Bit 2

T0IF

Bit 1

INTF

Bit 0

RBIF

Value on:

POR,

BOR

0000 000x

xxxx xxxx

Value on

all other

resets

0000 000u

uuuu uuuu

x--- u000

0Bh, 8Bh,

INTCON

10Bh, 18Bh

10Dh

10Fh

10Ch

10Eh

18Ch

18Dh

8Dh

0Dh

EEADR

EEADRH

EEDATA

EEDATH

EECON1

EECON2

PIE2

PIR2

EEPROM address register

鈥?/div>

EEPROM address high

xxxx xxxx

EEPROM data resister

鈥?/div>

EEPGD

鈥?/div>

EEPROM data resister high

鈥?/div>

WRERR

WREN

xxxx xxxx

x--- x000

EEPROM control resister2 (not a physical resister)

鈥?/div>

(1)

鈥?/div>

EEIE

EEIF

BCLIE

BCLIF

鈥?/div>

CCP2IE

CCP2IF

-r-0 0--0

Legend:

= unknown,

= unchanged, r = reserved,

= unimplemented read as 鈥?鈥? Shaded cells are not used during FLASH/

EEPROM access.

Note 1:

These bits are reserved; always maintain these bits clear.

DS30292B-page 46

漏

1999 Microchip Technology Inc.

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