PIC16F87X Datasheet

IC型号：
PIC16F87X
PDF描述：
28/40-pin 8-Bit CMOS FLASH Microcontrollers
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1377.31KB
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PIC16F87X

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral modules for controlling the

desired operation of the device. These registers are

implemented as static RAM. A list of these registers is

given in Table 2-1.

The Special Function Registers can be classified into

two sets; core (CPU) and peripheral. Those registers

associated with the core functions are described in

detail in this section. Those related to the operation of

the peripheral features are described in detail in the

peripheral feature section.

TABLE 2-1:

Addres

Bank 0

00h

(4)

01h

02h

(4)

03h

(4)

SPECIAL FUNCTION REGISTER SUMMARY

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(2)

Name

INDF

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PORTC

PORTD

PORTE

PCLATH

INTCON

PIR1

PIR2

TMR1L

TMR1H

T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

ADRESH

ADCON0

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 module鈥檚 register

Program Counter's (PC) Least Significant Byte

IRP

RP1

RP0

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

--0x 0000 --0u 0000

xxxx xxxx uuuu uuuu

04h

(4)

05h

06h

07h

08h

(5)

09h

(5)

0Ah

(1,4)

0Bh

(4)

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

Indirect data memory address pointer

鈥?/div>

PORTA Data Latch when written: PORTA pins when read

PORTB Data Latch when written: PORTB pins when read

PORTC Data Latch when written: PORTC pins when read

PORTD Data Latch when written: PORTD pins when read

鈥?/div>

GIE

PSPIF

(3)

鈥?/div>

PEIE

ADIF

(6)

鈥?/div>

T0IE

RCIF

鈥?/div>

RE2

RE1

RE0

---- -xxx ---- -uuu

---0 0000 ---0 0000

0000 000x 0000 000u

0000 0000 0000 0000

-r-0 0--0 -r-0 0--0

xxxx xxxx uuuu uuuu

Write Buffer for the upper 5 bits of the Program Counter

INTE

TXIF

EEIF

RBIE

SSPIF

BCLIF

T0IF

CCP1IF

鈥?/div>

INTF

TMR2IF

鈥?/div>

RBIF

TMR1IF

CCP2IF

Holding register for the Least Significant Byte of the 16-bit TMR1 register

Holding register for the Most Significant Byte of the 16-bit TMR1 register

鈥?/div>

WCOL

鈥?/div>

T1CKPS1

T1CKPS0

TOUTPS1

CKP

T1OSCEN

TOUTPS0

SSPM3

T1SYNC

TMR1CS

TMR1ON

Timer2 module鈥檚 register

TOUTPS3 TOUTPS2

SSPOV

SSPEN

Synchronous Serial Port Receive Buffer/Transmit Register

SSPM2

SSPM1

SSPM0

Capture/Compare/PWM Register1 (LSB)

Capture/Compare/PWM Register1 (MSB)

鈥?/div>

SPEN

鈥?/div>

RX9

CCP1X

SREN

CCP1Y

CREN

CCP1M3

ADDEN

CCP1M2

FERR

CCP1M1

OERR

CCP1M0

RX9D

--00 0000 --uu uuuu

0000 0000 0000 0000

TMR2ON T2CKPS1 T2CKPS0

-000 0000 -000 0000

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

--00 0000 --00 0000

0000 000x 0000 000x

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

USART Transmit Data Register

USART Receive Data Register

Capture/Compare/PWM Register2 (LSB)

Capture/Compare/PWM Register2 (MSB)

鈥?/div>

CCP2X

CCP2Y

CCP2M3

CCP2M2

GO/

DONE

CCP2M1

CCP2M0

A/D Result Register High Byte

ADCS1

ADCS0

CHS2

CHS1

CHS0

鈥?/div>

ADON

--00 0000 --00 0000

xxxx xxxx uuuu uuuu

0000 00-0 0000 00-0

Legend:

= unknown,

= unchanged,

= value depends on condition, - = unimplemented read as 鈥?鈥? r = reserved.

Shaded locations are unimplemented, read as 鈥?鈥?

Note 1:

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.

These registers can be addressed from any bank.

PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as 鈥?鈥?

PIR2<6> and PIE2<6> are reserved on these devices; always maintain these bits clear.

漏

1999 Microchip Technology Inc.

DS30292B-page 15

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