PIC16F87X Datasheet

IC型号：
PIC16F87X
PDF描述：
28/40-pin 8-Bit CMOS FLASH Microcontrollers
文件大小：
1377.31KB
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PIC16F87X

SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h)

R/W-0

SMP

bit7

R/W-0

CKE

R-0

D/A

R-0

R/W

R-0

bit0

R = Readable bit

W = Writable bit

U = Unimplemented bit, read

as 鈥?鈥?/div>

- n = Value at POR reset

bit 7:

SMP:

Sample bit

SPI Master Mode

= Input data sampled at end of data output time

= Input data sampled at middle of data output time

SPI Slave Mode

SMP must be cleared when SPI is used in slave mode

In I

C master or slave mode:

Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)

Slew rate control enabled for high speed mode (400 kHz)

CKE:

SPI Clock Edge Select (Figure

9-4, Figure 9-5

and

Figure 9-6)

SPI Mode:

CKP = 0

= Transmit happens on transistion from active clock state to idle clock state

= Transmit happens on transistion from idle clock state to active clock state

CKP = 1

= Data transmitted on falling edge of SCK

= Data transmitted on rising edge of SCK

In I

C Master or Slave Mode:

= Input levels conform to SMBUS spec

= Input levels conform to I

C specs

D/A:

Data/Address bit (I

C mode only)

= Indicates that the last byte received or transmitted was data

= Indicates that the last byte received or transmitted was address

Stop bit

C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)

= Indicates that a stop bit has been detected last (this bit is '0' on RESET)

= Stop bit was not detected last

Start bit

C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)

= Indicates that a start bit has been detected last (this bit is '0' on RESET)

= Start bit was not detected last

R/W:

Read/Write bit information (I

C mode only)

This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to

the next start bit, stop bit or not ACK bit.

In I

C slave mode:

= Read

= Write

In I

C master mode:

= Transmit is in progress

= Transmit is not in progress.

Or鈥檌ng this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in IDLE mode.

UA:

Update Address (10-bit I

C mode only)

= Indicates that the user needs to update the address in the SSPADD register

= Address does not need to be updated

BF:

Buffer Full Status bit

Receive (SPI and I

C modes)

= Receive complete, SSPBUF is full

= Receive not complete, SSPBUF is empty

Transmit (I

C mode only)

= Data Transmit in progress (does not include the ACK and stop bits), SSPBUF is full

= Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty

bit 6:

bit 5:

bit 4:

bit 3:

bit 2:

bit 1:

bit 0:

DS30292A-page 64

漏

1999 Microchip Technology Inc.

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