鈥減in# 113.鈥?/div>
Active low. (1) SPI data transfer start in SPI slave mode. When SPIS_N
is high, the KS8995M is deselected and SPIQ is held in high impedance
state, a high-to-low transition to initiate the SPI data transfer; (2) Not
used in I2C master mode.
Serial bus configuration pin
If EEPROM is not present, the KS8995M will start itself with chip
default (00)...
Pin Config.
PS[1:0]=00
PS[1:0]=01
PS[1:0]=10
PS[1:0]=11
Serial Bus Configuration
I2C Master Mode for EEPROM
Reserved
SPI Slave Mode for CPU Interface
Factory Test Mode (BIST)
113
PS1
Ipd
114
115
116
117
118
Note:
1. P = Power supply
I = Input
O = Output
I/O = Bi-directional
Gnd = Ground
PS0
RST_N
GNDD
VDDC
TESTEN
Ipd
Ipu
Gnd
P
Ipd
Serial bus configuration pin. See
鈥減in# 113.鈥?/div>
Reset the KS8995M. Active low.
Digital ground
1.8V digital core V
DD
NC for normal operation. Factory test pin.
Ipu = Input w/ internal pull-up
Ipd = Input w/ internal pull-down
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise
PU = Strap pin pull-up
PD = Strap pin pull-down
Otri = Output tristated
NC = No Connect
December 2003
13
M9999-120403
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