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KS8995MI Datasheet

  • KS8995MI

  • Micrel Semiconductor [Integrated 5-Port 10/100 Managed Swit...

  • 268.27KB

  • MICREL

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KS8995M
Address
Name
Description
Mode
Default
Micrel
Register 2 (0x02): Global Control 0
7
6-4
Reserved
802.1p base priority
Reserved
Used to classify priority for incoming 802.1q packets.
鈥淯ser priority鈥?is compared against this value.
鈮?/div>
: classified as high priority.
< : classified as low priority.
1, enable PHY MII interface.
(Note: if not enabled, the switch will tri-state all outputs)
R/W
R/W
0x0
0x4
3
Enable PHY MII
R/W
Pin LED[5][1]
strap option.
Pull-down (0):
isolate. Pull-up
(1): Enable.
Note: LED[5][1]
has internal
pull-up.
0x1
2
Buffer share mode
1, buffer pool is shared by all ports. A port can use
more buffer when other ports are not busy.
0, a port is only allowed to use 1/5 of the buffer pool.
1 the switch will drop packets with 0x8808 in T/L
filed, or DA=01-80-C2-00-00-01.
0, the switch will drop packets qualified as
鈥渇low control鈥?packets.
1, link change from 鈥渓ink鈥?to 鈥渘o link鈥?will cause fast
aging (<800碌s) to age address table faster. After an
age cycle is complete, the age logic will return to
normal (300 + 75 seconds ). Note: If any port is
unplugged, all addresses will be automatically aged
out.
R/W
1
UNH mode
R/W
0
0
Link change age
R/W
0
Register 3 (0x03): Global Control 1
7
Pass all frames
1, switch all packets including bad ones. Used solely
for debugging purpose. Works in conjunction with
sniffer mode.
Reserved
0, will enable transmit flow control based on AN result.
1, will not enable transmit flow control regardless of
AN result.
R/W
0
6
5
Reserved
IEEE 802.3x Transmit
flow control disable
R/W
R/W
0
Pin PMRXD3
strap option.
Pull-down(0):
Enable tx flow
control. Pull-up (1):
Disable tx/rx
flow control.
Note: PMRXD3
has internal pull-
down.
Pin PMRXD3 strap
option. Pull-down
(0): Enable rx flow
control. Pull-up (1):
Disable tx/rx flow
control.
Note: PMRXD3
has internal pull-
down.
0
4
IEEE 802.3x Receive
flow control disable
0, will enable receive flow control based on AN result.
1, will not enable receive flow control regardless of
AN result.
Note: Bit 5 and bit 4 default values are controlled by
the same pin, but they can be programmed
independently.
R/W
3
Frame Length field check
1, will check frame length field in the IEEE packets.
If the actual length does not match, the packet will be
dropped. (for L/T < 1500)
R/W
M9999-120403
40
December 2003

KS8995MI 产品属性

  • 66

  • 集成电路 (IC)

  • 专用 IC

  • *

  • *

  • *

  • 表面贴装

  • 128-BFQFP

  • 128-PQFP（14x20）

  • 散装

  • 576-1020

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