KS8995M
Micrel
SPIS_N
SPIC
SPID
SPIQ
X
0
0
0
0
0
0
1
0
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
WRITE COMMAND
SPIS_N
SPIC
SPID
SPIQ
D7
D6
D5
D4
D4
D2
D1
D0
D7
D6
D5
WRITE ADDRESS
Byte 1
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Byte 2
Byte 3 ...
Byte N
Figure 10. SPI Multiple Write
SPIS_N
SPIC
SPID
SPIQ
X
0
0
0
0
0
0
1
1
A7
A6
A5
A4
A3
A2
A1
A0
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
READ COMMAND
SPIS_N
SPIC
SPID
SPIQ
X
D7
READ ADDRESS
Byte 1
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
Byte 2
Byte 3
Byte N
Figure 11. SPI Multiple Read
MII Management Interface (MIIM)
A standard MIIM interface is provided for all five PHY devices in the KS8995M. An external device with MDC/MDIO capability
is able to read PHY status or to configure PHY settings. For details on the MIIM interface standard please reference the IEEE
802.3 specification (section 22.2.4.5). The MIIM interface does not have access to all the configuration registers in the
KS8995M. It can only access the standard MII registers. See
鈥淢IIM Registers.鈥?/div>
The SPI interface, on the other hand, can be
used to access the entire KS8995M feature set.
M9999-120403
38
December 2003
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