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PIC16CE625 Datasheet

  • PIC16CE625

  • OTP 8-Bit CMOS MCU with EEPROM Data Memory

  • 1208.41KB

  • 113页

  • Microchip

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PIC16CE62X
5.0
I/O PORTS
Note:
The PIC16CE62X parts have two ports, PORTA and
PORTB. Some pins for these I/O ports are multiplexed
with an alternate function for the peripheral features on
the device. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin.
On reset, the TRISA register is set to all
inputs. The digital inputs are disabled and
the comparator inputs are forced to ground
to reduce excess current consumption.
5.1
PORTA and TRISA Registers
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins con铿乬ured as inputs
when using them as comparator inputs.
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the V
REF
pin is a
very high impedance output. The user must con铿乬ure
TRISA<2> bit as an input and use high impedance
loads.
In one of the comparator modes de铿乶ed by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
cleared to enable outputs to use this function.
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input
and an open drain output. Port RA4 is multiplexed with the
T0CKI clock input. All other RA port pins have Schmitt
Trigger input levels and full CMOS output drivers. All pins
have data direction bits (TRIS registers) which can con铿乬-
ure these pins as input or output.
A '1' in the TRISA register puts the corresponding output
driver in a hi- impedance mode. A '0' in the TRISA register
puts the contents of the output latch on the selected pin(s).
Reading the PORTA register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are 铿乺st read, then this
value is modi铿乪d and written to the port data latch.
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(comparator control register) register and the VRCON
(voltage reference control register) register. When
selected as a comparator input, these pins will read
as '0's.
EXAMPLE 5-1:
CLRF
PORTA
INITIALIZING PORTA
;Initialize PORTA by setting
;output data latches
MOVLW 0X07
;Turn comparators off and
MOVWF CMCON
;enable pins for I/O
;functions
BSF
STATUS, RP0 ;Select Bank1
MOVLW 0x1F
;Value used to initialize
;data direction
MOVWF TRISA
;Set RA<4:0> as inputs
;TRISA<7:5> are always
;read as '0'.
FIGURE 5-1:
Data
bus
WR
PortA
BLOCK DIAGRAM OF
RA1:RA0 PINS
Q
V
DD
FIGURE 5-2:
Data
bus
WR
PortA
D
CK
D
WR
TRISA
BLOCK DIAGRAM OF RA2 PIN
Q
V
DD
Q
Q
N
RA2 Pin
Q
V
SS
Analog
Input Mode
Schmitt Trigger
Input Buffer
Q
EN
D
P
D
CK
D
Data Latch
Q
Q
P
Data Latch
I/O Pin
WR
TRISA
N
CK
Q
V
SS
Analog
Input Mode
TRIS Latch
CK
TRIS Latch
RD TRISA
RD TRISA
Schmitt Trigger
Input Buffer
Q
EN
RD PORTA
D
RD PORTA
To Comparator
V
ROE
V
REF
Note: I/O pins have protection diodes to V
DD
and V
SS
.
To Comparator
Note: I/O pins have protection diodes to V
DD
and V
SS
.
漏
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 23

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