PIC16CE625 Datasheet

IC型号：
PIC16CE625
PDF描述：
OTP 8-Bit CMOS MCU with EEPROM Data Memory
文件大小：
1208.41KB
PDF页数：
113页
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PIC16CE62X

11.0

INSTRUCTION SET SUMMARY

Each PIC16CE62X instruction is a 14-bit word divided

into an OPCODE which speci铿乪s the instruction type

and one or more operands which further specify the

operation of the instruction. The PIC16CE62X instruc-

tion set summary in Table 11-2 lists

byte-oriented,

bit-oriented,

and

literal and control

operations.

Table 11-1 shows the opcode 铿乪ld descriptions.

For

byte-oriented

instructions, 'f' represents a 铿乴e

designator. The 铿乴e register designator speci铿乪s which

铿乴e register is to be used by the instruction.

The destination designator speci铿乪s where the result of

the operation is to be placed. If 'd' is zero, the result is

placed in the W register. If 'd' is one, the result is placed

in the 铿乴e register speci铿乪d in the instruction.

For

bit-oriented

instructions, 'b' represents a bit 铿乪ld

designator which selects the number of the bit affected

by the operation, while 'f' represents the number of the

铿乴e in which the bit is located.

For

literal and control

operations, 'k' represents an

eight or eleven bit constant or literal value.

The instruction set is highly orthogonal and is grouped

into three basic categories:

鈥?/div>

Byte-oriented

operations

鈥?/div>

Bit-oriented

operations

鈥?/div>

Literal and control

operations

All instructions are executed within one single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of an

instruction. In this case, the execution takes two

instruction cycles with the second cycle executed as a

NOP. One instruction cycle consists of four oscillator

periods. Thus, for an oscillator frequency of 4 MHz, the

normal instruction execution time is 1

碌s.

If a

conditional test is true or the program counter is

changed as a result of an instruction, the instruction

execution time is 2

碌s.

Table 11-1 lists the instructions recognized by the

MPASM assembler.

Figure 11-1 shows the three general formats that the

instructions can have.

Note:

To maintain upward compatibility with

future PICmicro鈩?products, do not use the

OPTION

and

TRIS

instructions.

TABLE 11-1:

Field

OPCODE FIELD

DESCRIPTIONS

Description

All examples use the following format to represent a

hexadecimal number:

0xhh

where h signi铿乪s a hexadecimal digit.

Working register (accumulator)

Bit address within an 8-bit 铿乴e register

Literal 铿乪ld, constant data or label

FIGURE 11-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented

铿乴e register operations

8 7 6

OPCODE

f (FILE #)

d = 0 for destination W

d = 1 for destination f

f = 7-bit 铿乴e register address

Bit-oriented

铿乴e register operations

10 9

7 6

OPCODE

b (BIT #)

f (FILE #)

b = 3-bit bit address

f = 7-bit 铿乴e register address

Literal and control

operations

General

OPCODE

k = 8-bit immediate value

CALL

and

GOTO

instructions only

OPCODE

k (literal)

Don't care location (= 0 or 1)

The assembler will generate code with x = 0. It is the

recommended form of use for compatibility with all

Microchip software tools.

Destination select; d = 0: store result in W,

d = 1: store result in 铿乴e register f.

Default is d = 1

label

Label name

TOS

GIE

WDT

dest

[ ]

Top of Stack

Program Counter

Global Interrupt Enable bit

Watchdog Timer/Counter

Time-out bit

Power-down bit

Destination either the W register or the speci铿乪d

Options

Contents

Assigned to

In the set of

PCLATH

Program Counter High Latch

( )

鈫?/div>

鈭?/div>

talics

User de铿乶ed term (font is courier)

k = 11-bit immediate value

漏

1998 Microchip Technology Inc.

Preliminary

DS40182A-page 65

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