您的位置：维库电子市场网 > Datasheet > PIC16CE625

PIC16CE625 Datasheet

  • PIC16CE625

  • OTP 8-Bit CMOS MCU with EEPROM Data Memory

  • 1208.41KB

  • 113页

  • Microchip

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

PIC16CE62X
7.2
Using Timer0 with External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (T
OSC
)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.2.1
EXTERNAL CLOCK SYNCHRONIZATION
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4T
OSC
(and a small RC delay of
40 ns) divided by the prescaler value. The only
requirement on T0CKI high and low time is that they do
not violate the minimum pulse width requirement of
10 ns. Refer to parameters 40, 41 and 42 in the
electrical speci铿乧ation of the desired device.
7.2.2
TIMER0 INCREMENT DELAY
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 7-5). Therefore, it is necessary for T0CKI to be
high for at least 2T
OSC
(and a small RC delay of 20 ns)
and low for at least 2T
OSC
(and a small RC delay of
20 ns). Refer to the electrical speci铿乧ation of the
desired device.
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the TMR0 is
actually incremented. Figure 7-5 shows the delay from
the external clock edge to the timer incrementing.
FIGURE 7-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Small pulse
misses sampling
External Clock Input or
Prescaler output
(2)
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input =
卤4Tosc
max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
漏
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 37

PIC16CE625相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！