PIC16CE625 Datasheet

  • PIC16CE625

  • OTP 8-Bit CMOS MCU with EEPROM Data Memory

  • 1208.41KB

  • 113页

  • Microchip

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PIC16CE62X
10.6
Context Saving During Interrupts
10.7
Watchdog Timer (WDT)
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt e.g. W register and STATUS
register. This will have to be implemented in software.
Example 10-1 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be de铿乶ed
in both banks and must be de铿乶ed at the same offset
from the bank base address (i.e., W_TEMP is de铿乶ed
at 0x70 in Bank 0 and it must also be de铿乶ed at 0xF0
in Bank 1). The user register, STATUS_TEMP, must be
de铿乶ed in Bank 0. The Example 10-1:
Stores the W register
Stores the STATUS register in Bank 0
Executes the ISR code
Restores the STATUS (and bank select bit
register)
鈥?Restores the W register
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
The watchdog timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the CLKIN pin. That means that the WDT will run, even
if the clock on the OSC1 and OSC2 pins of the device
has been stopped, for example, by execution of a
SLEEP
instruction. During normal operation, a WDT
time-out generates a device RESET. If the device is in
SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the con-
铿乬uration bit WDTE as clear (Section 10.1).
10.7.1
WDT PERIOD
EXAMPLE 10-1: SAVING THE STATUS AND
W REGISTERS IN RAM
MOVWF
SWAPF
BCF
MOVWF
:
:
:
SWAPF
STATUS_TEMP,W
;swap STATUS_TEMP register
;into W, sets bank to original
;state
;move W into STATUS register
;swap W_TEMP
;swap W_TEMP into W
(ISR)
W_TEMP
STATUS,W
STATUS,RP0
STATUS_TEMP
;copy W to temp register,
;could be in either bank
;swap status to be saved into W
;change to bank 0 regardless
;of current bank
;save status to bank 0
;register
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, V
DD
and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The
CLRWDT
and
SLEEP
instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
10.7.2
WDT PROGRAMMING CONSIDERATIONS
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
It should also be taken in account that under worst case
conditions (V
DD
= Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 61

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