PIC16F8X
FIGURE 6-3:
TMR0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
Fetch
TMR0
T0
PC-1
PC
MOVWF TMR0
PC+1
MOVF TMR0,W
PC+2
MOVF TMR0,W
PC+3
MOVF TMR0,W
PC+4
MOVF TMR0,W
PC+5
MOVF TMR0,W
PC+6
T0+1
NT0
NT0+1
Instruction
Execute
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
FIGURE 6-4:
TMR0 INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT
(3)
TMR0 timer
T0IF bit 4
(INTCON<2>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC
Inst (PC)
Inst (PC-1)
PC +1
Inst (PC+1)
Dummy cycle
Interrupt Latency
(2)
PC +1
0004h
Inst (0004h)
Dummy cycle
0005h
Inst (0005h)
Inst (0004h)
FEh
1
FFh
1
00h
01h
02h
Inst (PC)
Note 1: T0IF interrupt 铿俛g is sampled here (every Q1).
2: Interrupt latency = 3.25Tcy, where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
4: The timer clock (after the synchronizer circuit) which increments the timer from FFh to 00h immediately sets the T0IF bit.
The TMR0 register will roll over 3 Tosc cycles later.
DS30430C-page 28
漏
1998 Microchip Technology Inc.