鈫?/div>
(destination<3:0>)
None
00
Status Affected: C, DC, Z
Subtract (2鈥檚 complement method) W reg-
ister from register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
1110
dfff
ffff
Words:
Cycles:
Q Cycle Activity:
1
1
Q1
Decode
The upper and lower nibbles of register
'f' are exchanged. If 'd' is 0 the result is
placed in W register. If 'd' is 1 the result
is placed in register 'f'.
Words:
Q2
Read
register 'f'
1
1
Q1
Decode
Q3
Process
data
Q4
Write to
destination
Cycles:
Q Cycle Activity:
Q2
Read
register 'f'
Q3
Process
data
Q4
Write to
destination
Example 1:
SUBWF
Before Instruction
REG1
W
C
Z
=
=
=
=
REG1,1
Example
3
2
?
?
SWAPF REG,
0
Before Instruction
REG1
=
0xA5
After Instruction
REG1
W
=
=
0xA5
0x5A
After Instruction
REG1
W
C
Z
=
=
=
=
1
2
1; result is positive
0
Example 2:
Before Instruction
REG1
W
C
Z
=
=
=
=
2
2
?
?
TRIS
Syntax:
Operands:
Operation:
Encoding:
Description:
Load TRIS Register
[label]
5
鈮?/div>
f
鈮?/div>
7
(W)
鈫?/div>
TRIS register f;
00
TRIS
f
After Instruction
REG1
W
C
Z
=
=
=
=
0
2
1; result is zero
1
Status Affected: None
0000
0110
0fff
The instruction is supported for code
compatibility with the PIC16C5X prod-
ucts. Since TRIS registers are read-
able and writable, the user can directly
address them.
Example 3:
Before Instruction
REG1
W
C
Z
=
=
=
=
1
2
?
?
Words:
Cycles:
Example
1
1
To maintain upward compatibility
with future PIC16CXX products,
do not use this instruction.
After Instruction
REG1
W
C
Z
=
=
=
=
0xFF
2
0; result is negative
0
漏
1998 Microchip Technology Inc.
DS30430C-page 67
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